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Microcomputer Components
SAB 80C517/80C537 8-Bit CMOS Single-Chip Microcontroller
User's Manual 05.94
Edition 05.95 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
Revision History
SAB 80C517/80C537 User's Manual Revision History: 04.95 Previous Releases: Page 119 133 141 167 188 360 06.91/10.92/08.93/04.94
Subjects (changes since last revision) Figure 7-33, writing error corrected Pin assignment Table 7-10 corrected Page number reference number corrected Software watchdog timer start: extended description Description of CTF flag modified ROM verification timing: text added
Semiconductor Group
4
80C517/80C537
Table of Contents
Page
1 2 3 3.1 3.2 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.1.1 6.1.2 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.4.1 7.1.4.2 7.1.4.3 7.2 7.2.1 7.2.1.1 7.2.1.2 7.2.1.3 7.2.1.4 7.2.2 7.2.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Eight Datapointers for Faster External Bus Access . . . . . . . . . . . . . . . . . . . .29 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . .33 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Hardware Reset and Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Reset Function and Circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Reset Output Pin (RO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . .45 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Read-Modify-Write Feature of Ports 0 through 6 . . . . . . . . . . . . . . . . . . . . . .49 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Operating Modes of Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Multiprocessor Communication Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Baud Rates of Serial Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 New Baud Rate Generator for Serial Channel 0 . . . . . . . . . . . . . . . . . . . . . .58 Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Operating Modes of Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Semiconductor Group
5
80C517/80C537
Table of Contents
Page
7.2.2.2 7.2.2.3 7.2.2.4 7.2.3 7.2.3.1 7.2.3.2 7.2.3.3 7.2.3.4 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.4.1 7.4.1.1 7.4.1.2 7.4.2 7.4.3 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.4.1 7.5.4.2 7.5.5 7.5.5.1 7.5.5.2 7.5.6 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.7 7.7.1 7.7.2 7.7.3 7.8
Multiprocessor Communication Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Baud Rates of Serial Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 New Baud Rate Generator for Serial Channel 1 . . . . . . . . . . . . . . . . . . . . . .64 Detailed Description of the Operating Modes . . . . . . . . . . . . . . . . . . . . . . . .66 Mode 0, Synchronous Mode (Serial Interface 0) . . . . . . . . . . . . . . . . . . . . . .66 Mode 1/Mode B, 8-Bit UART (Serial Interfaces 0 and 1) . . . . . . . . . . . . . . . .67 Mode 2, 9-Bit UART (Serial Interface 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Mode 3 / Mode A, 9-Bit UART (Serial Interfaces 0 and 1) . . . . . . . . . . . . . . .68 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Function and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 lnitialization and Input Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Start of Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Reference Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A/D Converter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 The Compare/Capture Unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 The Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Compare Function in the CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Compare Modes of the CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Timer/Compare Register Configurations in the CCU . . . . . . . . . . . . . . . . . .107 Compare Function of Timer 2 with Registers CRC, CC1 to CC4 . . . . . . . . .108 Compare Function of Registers CM0 to CM7 . . . . . . . . . . . . . . . . . . . . . . .116 Capture Function in the CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Programming the MDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Multiplication/Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Normalize and Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 The Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 The Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Slow-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Fail Save Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Semiconductor Group
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80C517/80C537
Table of Contents
Page
7.8.1 7.8.2 7.9 7.10 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3
Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Introduction to the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
10 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 10.1 Application Examples for the Compare Functions . . . . . . . . . . . . . . . . . . . .256 10.1.1 Generation of Two Different PWM Signals with "Additive Compare" using the "CCx Registers" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 10.1.2 Sine-Wave Generation with a CMx Registers/Compare Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 10.2 Using an SAB 80C537 with External Program Memory and Additional External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 11 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Semiconductor Group
7
Introduction
1
Introduction
The SAB 80C517/80C537 is a high-end microcontroller in the Siemens SAB 8051 8-bit microcontroller family. lt is based on the well-known industry standard 8051 architecture; a great number of enhancements and new peripheral features extend its capabilities to meet the extensive requirements of new applications. Nevertheless, the SAB 80C517 maintains compatibility within the Siemens SAB 8051 family; in fact, the SAB 80C517 is a superset of the Siemens SAB 80C515/ 80C535 microcontroller thus offering an easy upgrade path for SAB 80(C)515/80(C)535 users. In addition to all features of the SAB 80C515, there are several enhancements for higher performance. The SAB 80C517 has been expanded e.g. in its arithmetic characteristics, fail save mechanisms, analog signal processing facilities and timer capabilities. Listed below is a summary of the main features of the SAB 80C517/80C537:
q q q q q q q q q
q q
q q q q
8 Kbyte on-chip program memory (SAB 80C517 only) ROMIess version also available (SAB 80C537) Full compatibility with SAB 80C515/80C535 256 byte on-chip RAM 256 directly addressable bits 1 microsecond instruction cycle at 12-MHz oscillator frequency 64 of 111 instructions are executed in one instruction cycle External program and data memory expandable up to 64 Kbyte each 8-bit A/D converter - 12 multiplexed inputs - Programmable reference voltages - External/internal start of conversion Two 16-bit timers/counters (8051 compatible) Powerful compare/capture unit (CCU) based on a 16-bit timer/counter and a high-speed 16-bit timer for fast compare functions - One 16-bit reload/compare/capture register - Four 16-bit compare/capture registers, one of which serves up to nine compare channels (concurrent compare) Eight fast 16-bit compare registers Arithmetic unit for division, multiplication, shift and normalize operations Eight datapointers instead of one for indirect addressing of program and external data memory Extended watchdog facilities - 16-bit programmable watchdog timer - Oscillator watchdog
Semiconductor Group
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Introduction
q Nine ports
q q q
q q
- Seven bidirectional 8-bit ports - One 8-bit and one 4-bit input port for analog and digital input signals Two full-duplex serial interfaces with own baud rate generators Four priority level interrupt systems, 14 interrupt vectors Three power saving modes - Slow-down mode - Idle mode - Power-down mode Siemens high-performance ACMOS technology P-LCC-84 package
The ROMIess version SAB 80C537 is identical with the SAB 80C517 except for the fact that it lacks the on-chip program memory; the SAB 80C537 is designed for applications with external program memory. In this manual, any reference made to the SAB 80C517 applies to both versions, the SAB 80C517 and the SAB 80C537, unless otherwise noted. Figure 1-1 shows the logic symbol of the SAB 80C517:
Figure 1-1 Logic Symbol Semiconductor Group 9
Fundamental Structure
2
Fundamental Structure
The SAB 80C517 is a totally 8051-compatible microcontroller while its peripheral performance has been increased significantly. lt includes the complete SAB 80(C)515, providing 100% upward compatibility. This means that all existing 80515 programs or user's program libraries can be used further on without restriction and may be easily extended to the new SAB 80C517. The SAB 80C517 is in the Siemens line of highly integrated microcontrollers for control applications. Some of the various on-chip peripherals have been added to support the 8-bit core in case of stringent real-time requirements. The 32-bit/16-bit arithmetic unit, the improved 4-level interrupt structure and the increased number of eight 16-bit datapointers are meant to give such a CPU support. But strict compatibility to the 8051 architecture is a principle of the SAB 80C517's design. Furthermore, the SAB 80C517 contains three additional 8-bit I/O ports and twelve general input lines. The additional serial channel is compatible to an 8051-UART and provided with an independent and freely programmable baud rate generator. An 8-bit resolution A/D-converter with software-adjustable reference voltages has been integrated to allow analog signal processing. As a counterpart to the A/D converter, the SAB 80C517 includes a powerful compare/capture unit with two 16-bit timers for all kinds of digital signal processing. The controller has been completed with well considered provisions for "fail-safe" reaction in critical applications and offers all CMOS features like low power consumption as well as an idle, power-down and slow-down mode. Figure 2-1 shows a block diagram of the SAB 80C517. Readers who are familiar with the SAB 8051 or SAB 80515 may concentrate on chapters 6 and 7 where the reset conditions and the new peripheral components are described. Chapter 8 (Interrupt System) has a special section for 80515 professionals where enhancements of the interrupt structure compared to the SAB 80515 are summarized. For readers, however, who are newcomers to the 8051 family of microcontrollers, the following section may give a general view of the basic characteristics of the SAB 80C517. The details of operation are described later in chapters 3 and 4.
Semiconductor Group
10
Fundamental Structure
Figure 2-1 Functional Block Diagram Semiconductor Group 11
Fundamental Structure
Central Processing Unit The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes, are performed in one, two or four machine cycles. One machine cycle requires twelve oscillator cycles. The instruction set has extensive facilities for data transfer, logic and arithmetic instructions. The Boolean processor has its own full-featured and bit-based instructions within the instruction set. The SAB 80C517 uses five addressing modes: direct access, immediate, register, register indirect access, and for accessing the external data or program memory portions a base register plus indexregister indirect addressing. Memory Organization The SAB 80C517 has an internal ROM of 8 Kbyte. The program memory can externally be expanded up to 64 Kbyte (see Bus Expansion Control). The internal RAM consists of 256 bytes. Within this address space there are 128 bit-addressable locations and four register banks, each with 8 general purpose registers. In addition to the internal RAM there is a further 128-byte address space for the special function registers, which are described in sections to follow. Because of its Harvard architecture, the SAB 80C517 distinguishes between an external program memory portion (as mentioned above) and up to 64 Kbyte external data memory accessed by a set of special instructions. As an important improvement of the 8051 architecture, the SAB 80C517 contains eight datapointers (instead of one in the 8051) which speed up external data access. Bus Expansion Control The external bus interface of the SAB 80C517 consists of an 8-bit data bus (port 0), a 16-bit address bus (port 0 and port 2) and five control lines. The address latch enable signal (ALE) is used to demultiplex address and data of port 0. The program memory is accessed by the program store enable signal (PSEN) twice a machine cycle. A separate external access line (EA) is used to inform the controller while executing out of the lower 8 Kbyte of the program memory, whether to operate out of the internal or external program memory. The read or write strobe (RD, WR) is used for accessing the external data memory. Peripheral Control All on-chip peripheral components - I/O ports, serial interfaces, timers, compare/capture registers, the interrupt controller and the A/D converter - are handled and controlled by the so-called special function registers. These registers constitute the easy-to-handle interface with the peripherals. This peripheral control concept, as implemented in the SAB 8051, provides the high flexibility for further expansion as done in the SAB 80C517. Moreover some of the special function registers, like accumulator, Bregister, program status word (PSW), stack pointer (SP) and the data pointers (DPTR) are used by the CPU and maintain the machine status.
Semiconductor Group
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Central Processing Unit
3 3.1
Central Processing Unit General Description
The CPU (Central Processing Unit) of the SAB 80C517 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers, and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations of set, clear, complement, jump-if-not-set, jump-if-set-andclear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The A, B and PSW registers are described in section 4.4. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The PC is manipulated by the control transfer instructions listed in the chapter "Instruction Set". The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.
Semiconductor Group
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Central Processing Unit
3.2
CPU Timing
A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logical operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 3-1 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. lf it is a two-byte instruction, the second is read during S4 of the same machine cycle. lf it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next opcode) is ignored, and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 3-1 a) and b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most SAB 80C517 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figures 3-1 c) and d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.
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Central Processing Unit
Figure 3-1 Fetch/Execute Sequence Semiconductor Group 15
Memory Organization
4
Memory Organization
The SAB 80C517 CPU manipulates operands in the following four address spaces: - - - - 4.1 up to 64 Kbyte of program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128-byte special function register area Program Memory
The program memory of the SAB 80C517 consists of an internal and an external memory portion (see figure 4-1). 8 Kbytes of program memory may reside on-chip (SAB 80C517 only), while the SAB 80C537 has no internal ROM. The program memory can be externally expanded up to 64 Kbyte. lf the EA pin is held high, the SAB 80C517 executes out of the internal program memory unless the address exceeds 1 FFFH. Locations 2000H through 0FFFFH are then fetched from the external program memory. lf the EA pin is held low, the SAB 80C517 fetches all instructions from the external program memory. Since the SAB 80C537 has no internal program memory, pin EA must be tied low when using this device. In either case, the 16-bit program counter is the addressing mechanism. Locations 03H through 93H in the program memory are used by interrupt service routines. 4.2 Data Memory
The data memory address space consists of an internal and an external memory portion. Internal Data Memory The internal data memory address space is divided into three physically separate and distinct blocks: the lower 128 byte of RAM, the upper RAM area, and the 128-byte special function register (SFR) area (see figure 4-2). While the latter SFR area and the upper RAM area share the same address locations, they must be accessed through different addressing modes. The map in figure 4-2 and the following table show the addressing modes used for the different RAM/SFR spaces.
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Memory Organization
Address Space Lower 128 bytes of RAM Upper 128 bytes of RAM Special function registers
Locations 00H to 7FH 80H to 0FFH 80H to 0FFH
Addressing Mode direct/indirect indirect direct
For details about the addressing modes see chapter 9.1.
Figure 4-1 Program Memory Address Space The lower 128 bytes of the internal RAM are again grouped in three address spaces (see figure 4-3): 1) 2) A general purpose register area occupies locations 0 trough 1FH (see also section 4.3). The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bits. (Programming information: These bits can be referred to in two ways, both of which are acceptable for the ASM51. One way is to refer to their addresses, i.e. 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus bits 0 to 7 can also be referred to as bits 20.0-20.7, and bits 8-0FH are the same as 21.0-21.7 and so on. Each of the 16 bytes in this segment may also be addressed as a byte.) Locations 30H to 7FH can be used as a scratch pad area.
3)
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Memory Organization
Using the stack pointer (SP) - a special function register described in section 4.4 - the stack can be located anywhere in the whole internal data memory address space. The stack depth is limited only by the internal RAM available (256 byte maximum). However, pay attention to the fact that the stack is not overwritten by other data, and vice versa. External Data Memory Figure 4-2 and 4-3 contain memory maps which illustrate the internal/external data memory. To address data memory external to the chip, the "MOVX" instructions in combination with a 16-bit datapointer or an 8-bit general purpose register are used. Refer to chapter 9 (Instruction Set) or 5 (External Bus Interface) for detailed descriptions of these operations. A maximum of 64 Kbytes of external data memory can be accessed by instructions using a 16-bit address. The datapointer structure in the SAB 80C517 deserves special attention, since it consists of eight 16-bit registers which can be alternatively selected as datapointers. See section 4.4 and chapter 5 for further details.
Figure 4-2 Data Memory / SFR Address Spaces
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Memory Organization
Figure 4-3 Mapping of the Lower Portion of the Internal Data Memory Semiconductor Group 19
Memory Organization
4.3
General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, PSW.3 and PSW.4, select the active register bank (see description of the PSW). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. ASM51 and the device SAB 80C517 default to register bank 0. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction of code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. 4.4 Special Function Registers
The special function register (SFR) area has two important functions. Firstly, all CPU registers except the program counter and the four register banks reside here. The CPU registers are the arithmetic registers like A, B, PSW and pointers like SP, DPHx and DPLx. Secondly, a number of registers constitute the interface between the CPU and all on-chip peripherals. That means, all control and data transfers from and to the peripherals use this register interface exclusively. The special function register area is located in the address space above the internal RAM from addresses 80H to FFH. All 81 special function registers of the SAB 80C517 reside here. Sixteen SFRs, that are located on addresses dividable by eight, are bit-addressable, thus allowing 128 bit-addressable locations within the SFR area. Since the SFR area is memory mapped, access to the special function registers is as easy as with the internal RAM, and they may be processed with most instructions. In addition, if the special functions are not used, some of them may be used as general scratch pad registers. Note, however, all SFRs can be accessed by direct addressing only. The special function registers are listed in the following tables where they are organized in functional groups which refer to the functional blocks of the SAB 80C517. Block names and symbols are listed in alphabetical order. Bit addressable special function registers are marked with a dot in the fifth column. Special function registers with bits belonging to more then one functional block are marked with an asterisk at the symbol name.
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Memory Organization
Special Function Registers of the SAB 80C517 Block CPU Symbol ACC B DPH DPL DPSEL PSW SP ADCON0 ADCON1 ADDAT DAPR IEN0 CTCON 2) IEN1 IEN2 IP0 IP1 IRCON TCON 2) T2CON 2) ARCON MD0 MD1 MD2 MD3 MD4 MD5 Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register D/A Converter Program Register Interrupt Enable Register 0 Com. Timer Control Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Timer Control Register Timer 2 Control Register Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Address 0E0H 1) 0F0H 1) 83H 82H 92H 0D0H 1) 81H 0D8H 1) 0DCH 0D9H 0DAH 0A8H 1) 0E1H 0B8H 1) 9AH 0A9H 0B9H 0C0H 1) 88H 1) 0C8H 1) 0EFH 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH Contents after Reset 00H 00H 00H 00H XXXX.X000B 3) 00H 07H 00H XXXX.0000B 3) 00H 00H 00H 0XXX.0000B 3) 00H XXXX.00X0B 3) 00H XX00.0000B 3) 00H 00H 00H 0XXX.XXXXB 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3)
A/DConverter
Interrupt System
MUL/DIV Unit
1) Bit-addressable special function registers. 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate.
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Memory Organization
Special Function Registers of the SAB 80C517 (cont'd) Block Compare/ Capture Unit (CCU) Symbol CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL CTCON CTRELH CTRELL TH2 TL2 T2CON Name Compare/Capture Enable Register Compare/Capture 4 Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 4, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Compare/Capture Register 4, Low Byte Compare Enable Register Compare Register 0, High Byte Compare Register 1, High Byte Compare Register 2, High Byte Compare Register 3, High Byte Compare Register 4, High Byte Compare Register 5, High Byte Compare Register 6, High Byte Compare Register 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Com./Rel./Capt. Register, High Byte Com./Rel./Capt. Register, Low Byte Com. Timer Control Register Com. Timer Rel. Register, High Byte Com. Timer Rel. Register, Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Address 0C1H 0C9H 0C3H 0C5H 0C7H 0CFH 0C2H 0C4H 0C6H 0CEH 0F6H 0D3H 0D5H 0D7H 0E3H 0E5H 0E7H 0F3H 0F5H 0D2H 0D4H 0D6H 0E2H 0E4H 0E6H 0F2H 0F4H 0F7H 0CBH 0CAH 0E1H 0DFH 0DEH 0CDH 0CCH 0C8H 1) Contents after Reset 00H X000.0000B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0XXX.0000B 3) 00H 00H 00H 00H 00H
1) Bit-addressable special function registers. 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate.
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Memory Organization
Special Function Registers of the SAB 80C517 (cont'd) Block Ports Symbol P0 P1 P2 P3 P4 P5 P6 P7 P8 PCON ADCON0 2) PCON 2) S0BUF S0CON S0RELL4) S0RELH4) S1BUF S1CON S1REL S1RELH4) TCON TH0 TH1 TL0 TL1 TMOD IEN0 2) IEN1 2) IP0 2) IP1 2) WDTREL Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4Bit Power Control Register A/D Converter Control Register Power Control Register Serial Channel 0, Buffer Register Serial Channel 0 Control Register Serial Channel 0, Reload Reg., low byte Serial Channel 0, Reload Reg., high byte Serial Channel 1, Buffer Register Serial Channel 1, Control Register Serial Channel 1, Reload Register Serial Channel 1, Reload Reg., high byte Timer Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Watchdog Timer Reload Register Address 80H 1) 90H 1) 0A0H 1) 0B0H 1) 0E8H 1) 0F8H 1) 0FAH 0DBH 0DDH 87H 0D8H 1) 87H 99H 98H1) 0AAH 0BAH 9CH 9BH 9DH OBBH 88H 1) 8CH 8DH 8AH 8BH 89H 0A8H 1) 0B8H 1) 0A9H 0B9H 86H Contents after Reset FFH FFH FFH FFH FFH FFH FFH XXH 3) XXH 3) 00H 00H 00H XXH 3) 00H 0D9H XXXX.XX11B 3) XXH 3) 0X00.0000B 3) 00H XXXX.XX11B 00H 00H 00H 00H 00H 00H 00H 00H 00H XX00.0000B3) 00H
3)
Pow. Sav.M Serial Channels
Timer0/ Timer1
Watchdog
1) Bit-addressable special function registers. 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate. 4) These registers are available in the CA step and later steps.
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Memory Organization
The following paragraphs give a general overview of the special function registers and refer to sections where a more detailed description can be found. Accumulator, SFR Address 0E0H ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word Register (PSW), SFR Address 0D0H 0D7H 0D0H CY 0D6H AC 0D5H F0 0D4H RS1 0D3H RS0 0D2H OV 0D1H F1 0D0H P PSW
The PSW register contains program status information. Bit CY AC F0 RS1 0 0 1 1 OV F1 P RS0 0 1 0 1 Function Carry Flag Auxiliary carry flag (for BCD operations) General purpose user flag 0 Register bank select control bits Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH Overflow flag General purpose user flag 1 Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
B Register, SFR Address 0F0H The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register.
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Memory Organization
Stack Pointer, SFR Address 081H The stack pointer (SP) register is 8 bits wide. lt is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H above register bank zero. The SP can be read or written under software control. Datapointer, SFR Address 082H and 083H Datapointer Select Register, SFR Address 092H As a functional enhancement to standard 8051 controllers, the SAB 80C517 contains eight 16-bit registers which can be used as datapointers. To be compatible with 8051 architecture, the instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in special function register DPSEL (datapointer select register, address 92H). Each 16-bit datapointer (DPTRx) register is a concatenation of registers DPHx (data pointer's high order byte) and DPLx (data pointer's low order byte). These pointers are used in register-indirect addressing to move program memory constants and external data memory variables, as well as to branch within the 64-Kbyte program memory address space. Since the datapointers are mainly used to access the external world, they are described in more detail in section 5.2. Ports 0 to 8 P0 to P8 are the SFR latches to port 0 to 8, respectively. The port SFRs 0 to 5 are bit-addressable. Ports 0 to 6 are 8-bit I/O ports (that is in total 56 I/O lines) which may be used as general purpose ports and which provide alternate output functions dedicated to the on-chip peripherals of the SAB 80C517. Port 7 (8-bit) and port 8 (4-bit) are general purpose input ports and have no internal latch. That means, these port lines are used for the 12 multiplexed input lines of the A/D converter but can also be used as digital inputs. P7/P8 are the associated SFRs when the digital value is to be read by the CPU. Both ports can be read only. You can find more about the ports in section 7.1 (parallel I/O).
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Memory Organization
Peripheral Control, Data and Status Registers Most of the special function registers are used as control, status and data registers to handle the on-chip peripherals. In the special function register table the register names are organized in groups and each of these groups refer to one peripheral unit. More details on how to program these registers are given in the descriptions of the following peripheral units:
Unit Ports Serial channels Timer 0/1 A/D converter Compare/capture unit Arithmetic unit (MUL/DIV unit) Power saving control unit Watchdog unit Interrupt system
Symbol - - - ADC CCU MDU - WDT/OWD -
Section 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8
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External Bus Interface
5
External Bus Interface
The SAB 80C517 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed. To speed up external bus accesses, the SAB 80C517 contains eight 16-bit registers used as datapointers. This enhancement to the 8051 architecture is described in section 5.2. 5.1 Accessing External Memory
lt is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: Accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6, see section 7.1.). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described (for further details see chapter 7.1). Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes 0FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. lf an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. lt should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods.
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External Bus Interface
Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD/WR and information on port 0 and port 2, is illustrated in figure 5-2 a) and b). Data memory: In a write cycle, the data byte to be written appears on port 0 just before WR is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. For further information see section 5.3. External Program Memory Access The external program memory is accessed under two conditions: - whenever signal EA is active; or - whenever the program counter (PC) contains a number that is larger than 01FFFH This requires the ROMIess version SAB 80C537 to have EA wired low to allow the lower 8 K program bytes to be fetched from external memory. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). Since the SAB 80C537 has no internal program memory, accesses to program memory are always external, and port 2 is at all times dedicated to output the high-order address byte. This means that port 0 and port 2 of the SAB 80C537 can never be used as general-purpose I/O. This also applies to the SAB 80C517 when it is operated with only an external program memory.
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External Bus Interface
5.2
Eight Datapointers for Faster External Bus Access
The Importance of Additional Datapointers The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this datapointer and an increment instruction, any other pointer handling is to be done byte by byte. For complex applications with numerous external peripherals or extended data storage capacity this turned out to be a "bottle neck" for the 8051's communication to the external world. Especially programming in high-level languages (PLM51, "C", PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. How the Eight Datapointers of the SAB 80C517 are Realized Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility to the 8051 instruction set. This instruction set, however, allows the handling of only one single 16bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the SAB 80C517 contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user's program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the SAB 80C517 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment. Figure 5-1 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx.
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External Bus Interface
Figure 5-1 Accessing of External Data Memory via Multiple Datapointers Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte by byte. This not only takes more time, it also requires additional space in the internal RAM. Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: Start address of table in external RAM: 1FFFH 2FA0H
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External Bus Interface
1) Using only One Datapointer (Code for an 8051) Initialization Routine Action Initialize shadow_variables with source_pointer Initialize shadow_variables with destination_pointer Code MOV LOW(SRC_PTR), #0FFH MOV HIGH(SRC_PTR), #1FH MOV LOW(DES_PTR), #0A0H MOV HIGH(DES_PTR), #2FH
Table Look-up Routine under Real Time Conditions Action Save old datapointer Load Source Pointer Increment and check for end of table (execution time not relevant for this consideration) Fetch source data byte from ROM table Save source_pointer and load destination_pointer Code PUSH DPL PUSH DPH MOV DPL, LOW(SRC_PTR) MOV DPH, HIGH(SRC_PTR) INC DPTR CJNE... ... MOVC A,@DPTR MOV LOW(SRC_PTR), DPL MOV HIGH(SRC_PTR), DPH MOV DPL, LOW(DES_PTR) MOV DPH, HIGH(DES_PTR) INC DPTR MOVX @DPTR, A MOV LOW(DES_PTR), DPL MOV HIGH(DES_PTR),DPH POP DPH POP DPL - Machine Cycles 2 2 2 2 - - - 2 2 2 2 2 - 2 2 2 2 2 28
Increment destination_pointer (ex. time not relevant) Transfer byte to destination address Save destination_pointer Restore old datapointer Total execution time (machine cycles)
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External Bus Interface
2) Using Two Datapointers (Code for an SAB 80C517) Initialization Routine Action Initialize DPTR6 with source pointer Initialize DPTR7 with destination pointer Code MOV DPSEL, #06H MOV DPTR, #1FFFH MOV DPSEL, #07H MOV DPTR, #2FA0H
Table Look-up Routine under Real Time Conditions Action Save old source pointer Load source pointer Increment and check for end of table (execution time not relevant for this consideration) Fetch source data byte from ROM table Save source_pointer and load destination_pointer Transfer byte to destination address Save destination pointer and restore old datapointer Total execution time (machine cycles) Code PUSH DPSEL MOV DPSEL, #06H INC DPTR CJNE... ... MOVC A,@DPTR MOV DPSEL, #07H MOVX @DPTR, A POP DPSEL - Machine Cycles 2 2 - - - 2 2 2 2 12
The above example shows that utilization of the SAB 80C517's multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that an SAB 80C517 program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use.
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External Bus Interface
5.3
PSEN, Program Store Enable
The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 12 osillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 6 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 5-2 a) and b). 5.4 ALE, Address Latch Enable
The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 5-2 b) ). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. 5.5 Overlapping External Data and Program Memory Spaces
In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the SAB 80C517, the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
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External Bus Interface
Figure 5-2 a) and b) External Program Memory Execution Semiconductor Group 34
System Reset
6 6.1 6.1.1
System Reset Hardware Reset and Power-Up Reset Reset Function and Circuitries
The hardware reset function incorporated in the SAB 80C517 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode (see section 7.7) is to be terminated. Additionally to the hardware reset, which is applied externally to the SAB 80C517, there are two internal reset sources, the watchdog timer and the oscillator watchdog. They are described in detail in section 7.8 "Fail-Save Mechanisms". The chapter at hand only deals with the external hardware reset. The reset input is an active low input at pin 10 (RESET). An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle in which RESET is low and is repeated every cycle until RESET goes high again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the reset pin to VSS via a capacitor as shown in figure 6-1 a) and c). After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specified time below the upper threshold of the Schmitt trigger to effect a complete reset.
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System Reset
The time required is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is usually met using a capacitor of 4.7 to 10 microfarad. The same considerations apply if the reset signal is generated externally (figure 6-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive.
Figure 6-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. The default values of the special function registers (SFR) to which they are forced during reset are listed in table 6-1. After reset is internally accomplished the port latches of ports 0 to 6 default in 0FFH. This leaves port 0 floating, since it is an open drain port when not used as data/ address bus. All other I/O port lines (ports 1 through 6) output a one (1). Ports 7 and 8, which are input-only ports, have no internal latch and therefore the contents of the special function registers P7 and P8 depend on the levels applied to ports 7 and 8. The contents of the internal RAM of the SAB 80C517 is not affected by a reset. After power-up the contents is undefined, while it remains unchanged during a reset it the power supply is not turned off.
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System Reset
Table 6-1 Register PC ACC ADCON0 ADCON1 ADDAT ARCON B CCL1-4 CCH1-4 CCEN CC4EN CMEN CML0-7 CMH0-7 CMSEL CRCL, CRCH CTCON CTRELL, CTRELH DAPR DPSEL DPTR0-7 Contents 0000H 00H 00H XXXX 0000B 00H 0XXX XXXXB 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0XXX 0000B 00H 00H XXXX X000B 0000H Register IEN0, IEN1 IEN2 IP0 IP1 IRCON MD0-5 P0-P6 PCON PSW S0BUF, S1BUF S0CON S1CON S1REL SP TCON TL0, TH0 TL1, TH1 TL2, TH2 TMOD T2CON WDTREL - Contents 00H XXXX 00X0B 00H XX00.0000B 00H XXH 0FFH 00H 00H 0XXH 00H 0X00 0000B 00H 07H 00H 00H 00H 00H 00H 00H 00H -
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System Reset
6.1.2
Hardware Reset Timing
This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level at pin 10) the internal reset procedure is started. lt needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is not performed if there is no clock available at the device (This can be avoided using the oscillator watchdog, which provides an auxiliary clock for performing a correct reset without clock at the XTAL1 and XTAL2 pins. See section 7.8 for further details). The RESET signal must be active for at least two machine cycles; after this time the SAB 80C517 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 6-2 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles.
Figure 6-2 CPU Timing after Reset
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System Reset
6.2
Reset Output Pin (RO)
As mentioned before the SAB 80C517 internally synchronizes an external reset signal at pin RESET in order to perform a reset procedure. Additionally, the SAB 80C517 provides several "failsave" mechanisms, e.g. watchdog timer and oscillator watchdog, which can internally generate a reset, too. Thus, it is often important to inform also the peripherals external to the chip that a reset is being performed and that the controller will soon start its program again. For that purpose, the SAB 80C517 has a pin dedicated to output the internal reset request. This reset output (RO) at pin 82 shows the internal (and already synchronized) reset signal requested by any of the three possible sources in the SAB 80C517: external hardware reset, watchdog timer reset, oscillator watchdog reset. The duration of the active low signal of the reset output depends on the source which requests it. In the case of the external hardware reset it is the synchronized external reset signal at pin RESET. In the case of a watchdog timer reset or oscillator watchdog reset the RESET OUT signal takes at least two machine cycles, which is the minimal duration for a reset request allowed. For details - how the reset requests are OR-ed together and how long they last - see also chapter 7.8 "Fail-Save Mechanisms".
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7
On-Chip Peripheral Components
This chapter gives detailed information about all on-chip peripherals of the SAB 80C517 except for the integrated interrupt controller, which is described separately in chapter 8. Sections 7.1 and 7.2 are associated with the general parallel and serial I/O facilities while the remaining sections describe the miscellaneous functions such as the timers, A/D converter, compare/capture unit, multiplication/division unit, power saving modes, "fail-save" mechanisms, oscillator and clock circuitries and system clock output. 7.1 7.1.1 Parallel I/O Port Structures
Digital I/O The SAB 80C517 allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P6 are performed via their corresponding special function registers P0 to P6. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents (see also chapter 7.1.2 and chapter 5 for more details about the external bus interface). Digital/Analog Input Ports Ports 7 and 8 are available as input ports only and provide for two functions. When used as digital inputs, the corresponding SFR's P7 and P8 contain the digital value applied to port 7 and port 8 lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or a four-bit field in SFR ADCON1, as described in section 7.4. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR's P7 or P8; this will have no effect. lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications (VIL/VIH). Since P7 and P8 are not bit-addressable registers, all input lines of P7 or P8 are read at the same time by byte instructions.
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Nevertheless, it is possible to use ports 7 and 8 simultaneously for analog and digital input. However, care must be taken that all bits of P7 or P8 that have an undetermined value caused by their analog function are masked. In order to guarantee a high-quality A/D conversion, digital input lines of port 7 and port 8 should not toggle while a neighbouring port pin is executing an A/D conversion. This could produce crosstalk to the analog signal. Digital I/O Port Circuitry Figure 7-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 7 I/O-ports. The bit latch (one bit in the port's SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin self is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P6) activate the "read-latch" signal, while others activate the "read-pin" signal (see section 7.1.4.3).
Read Latch
Int. Bus Write to Latch
D Port Latch CLK
Q Port Driver Circuit Port Pin
Q
MCS01822
Read Pin
Figure 7-1 Basic Structure of a Port Circuitry
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Port 1 through 6 output drivers have internal pullup FET's (see figure 7-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit must contain a one (1) (that means for figure 7-2: Q = 0), which turns off the output driver FET n1. Then, for ports 1 through 6, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional".
Read Latch
VCC
Internal Pull Up Arrangement Q Bit Latch CLK Pin
Int. Bus Write to Latch
D
Q
n1
MCS01823
Read Pin
Figure 7-2 Basic Output Driver Circuit of Ports 1 through 6 In fact, the pullups mentioned before and included in figure 7-2 are pullup arrangements as shown in figure 7-3. One n-channel pulldown FET and three pullup FETs are used: - The pulldown FET n1 is of n-channel type. lt is a very strong driver transistor which is capable of sinking high currents (IOL); it is only activated if a "0" is programmed to the port pin. A short circuit to VCC must be avoided if the transistor is turned on, since the high current might destroy the FET. - The pullup FET p1 is of p-channel type. lt is activated for two oscillator periods (S1P1 and S1P2) if a 0-to-1 transition is programmed to the port pin, i.e. a "1" is programmed to the port latch which contained a "0". The extra pullup can drive a similar current as the pulldown FET n1. This provides a fast transition of the logic levels at the pin.
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- The pullup FET p2 is of p-channel type. lt is always activated when a "1" is in the port latch, thus providing the logic high output level. This pullup FET sources a much lower current than p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input level. - The pullup FET p3 is of p-channel type. lt is only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g. when used as input. In this configuration only the weak pullup FET p2 is active, which sources the current IIL. lf, in addition, the pullup FET p3 is activated, a higher current can be sourced (ITL). Thus, an additional power consumption can be avoided if port pins are used as inputs with a low level applied. However, the driving cabability is stronger if a logic high level is output.
Figure 7-3 Output Driver Circiut of Ports 1 through 6 The described activating and deactivating of the four different transistors translates into four states the pins can be: - - - - input low state (IL), p2 active only input high state (IH) = steady output high state (SOH), p2 and p3 active forced output high state (FOH), p1, p2 and p3 active output low state (OL), n1 active
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If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state. If the latch is loaded with "0", the pin will be in OL state. If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur. At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on pin is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will remain in this state or will switch to IH (= SOH) state. If it is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3's trip point after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds the drive capability of p2, the pin might remain in the IL state and provide a weak "1" until the first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of the external circuitry. The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities. Port 0, in contrast to ports 1 through 6, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 7-4 a) is used only when the port is emitting 1's during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to th port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. lf port 0 is configured as general I/O port and has to emit logic high level (1), external pullups are required.
Figure 7-4 a) Port 0 Circuitry Semiconductor Group 44
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7.1.2
Port 0 and Port 2 used as Address/Data Bus
As shown in figures 7-4 a) and 7-4 b), the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. lf the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P2 SFR remains unchanged while the P0 SFR has 1's written to it. Being an address/data bus, port 0 uses a pullup FET as shown in figure 7-4 a). When a 16-bit address is used, port 2 uses the additional strong pullups p1 to emit 1's for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity.
Figure 7-4 b) Port 2 Circuitry
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7.1.3
Alternate Functions
Several pins of ports 1, 3, 4, 5 and 6 are multifunctional. They are port pins and also serve to implement special features as listed in table 7-1. Figure 7-5 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pull-down FET is on and the port pin is stuck at 0. (This does not apply to ports 1.0 to 1.4 and ports 5.0 to 5.7 when operated in compare output mode; refer to section 7.5.3 for details). After reset all port latches contain ones (1).
Read Latch
Alternate Output Function
VCC
Internal Pull Up Arrangement Pin
Int. Bus Write to Latch
D Bit Latch CLK
Q
&
Q
MCS01827
Read Pin
Alternate Input Function
Figure 7-5 Circuitry of Ports 1, 3, 4, 5 and 6.0 through 6.2 Ports 6.3 through 6.7 have no alternate functions as discribed above. Therefore, the port circuitry can do without the switching capability between alternate function and normal I/O operation. This more simple circuitry is shown as basic port structure in figures 7-1 and 7-2.
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Table 7-1 Alternate Functions of Port Pins Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P6.0 P6.1 P6.2 Pin INT3/CC0 INT4/CC1 INT5/CC2 INT6/CC3 INT2/CC4 T2EX CLKOUT T2 RXD0 TXD0 INT0 INT1 T0 T1 WR RD CM0 CM1 CM2 CM3 CM4 CM5 CM6 CM7 CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 ADST RXD1 TXD1 Alternate Function Ext. interrupt 3/capture 0/compare 0 Ext. interrupt 4/capture 1/compare 1 Ext. interrupt 5/capture 2/compare 2 Ext. interrupt 6/capture 3/compare 3 Ext. interrupt 2/capture 4/compare 4 Timer 2 ext. reload trigger input System clock output Timer 2 external count input Serial input channel 0 Serial output channel 0 Ext. interrupt 0 Ext. interrupt 1 Timer 0 external count input Timer 1 external count input External data memory write strobe External data memory read strobe Compare 0 of compare unit CM0-7 Compare 1 of compare unit CM0-7 Compare 2 of compare unit CM0-7 Compare 3 of compare unit CM0-7 Compare 4 of compare unit CM0-7 Compare 5 of compare unit CM0-7 Compare 6 of compare unit CM0-7 Compare 7 of compare unit CM0-7 Concurrent compare 0 Concurrent compare 1 Concurrent compare 2 Concurrent compare 3 Concurrent compare 4 Concurrent compare 5 Concurrent compare 6 Concurrent compare 7 Ext. A/D converter start Serial input channel 1 Serial output channel 1
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7.1.4
Port Handling
7.1.4.1 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 7-6 illustrates this port timing. lt must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain requirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once.
Figure 7-6 Port Timing
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7.1.4.2 Port Loading and Interfacing The output buffers of ports 1 through 6 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be looked up in the DC characteristics in the Data Sheet of the SAB 80C517. The corresponding parameters are VOL and VOH. The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus. When used as inputs it must be noted that the ports 1 through 6 are not floating but have internal pullup transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters ITL and IIL in the DC characteristics specify these currents). Port 0 as well as the input only ports 7 and 8, however, have floating inputs when used for digital input. 7.1.4.3 Read-Modify-Write Feature of Ports 0 through 6 Some port-reading instructions read the latch and others read the pin (see figure 7-1). The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write" instructions, which are listed in table 7-2. lf the destination is a port or a port bit, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, resp., is performed by reading the SFR P0 to P6; for example, "MOV A, P3" reads the value from port 3 pins, while "ANL P4, #0AAH" reads from the latch, modifies the value and writes it back to the latch. lt is not obvious that the last three instructions in this list are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch.
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Table 7-2 Read-Modify-Write Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y, C CLR Px.y SETB Px.y Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit; e.g. CPL P3.0 Increment byte; e.g. INC P4 Decrement byte; e.g. DEC P5 Decrement and jump if not zero; e.g. DJNZ P3, LABEL Move carry bit to bit y of port x Clear bit y of port x Set bit y of port x
The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. lf the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor (approx. 0.7 V, i.e. a logic low level !) and interpret it as "0". For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch. However, reading the latch rather than the pin will return the correct value of "1".
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7.2
Serial Interfaces
The SAB 80C517 has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit and receive simultaneously. They are also receive buffered, meaning they can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still has not been read by the time reception of the second byte is complete, the last received byte will be lost). The serial channel 0 is completely compatible with the serial channel of the SAB 80(C)51. Serial channel 1 has the same functionality in its asynchronous modes, but the synchronous mode is lacking. 7.2.1 Serial Interface 0
7.2.1.1 Operating Modes of Serial Interface 0 The serial interface 0 can operate in four modes (one synchronous mode, three asynchronous modes). The baud rate clock for this interface is derived from the oscillator frequency (mode 0, 2) or generated either by timer 1 or by a dedicated baud rate generator (mode 1, 3). A more detailed description of how to set the baud rate will follow in section 7.2.1.3. Mode 0: Shift register (synchronous) mode: Serial data enters and exits through RXD0. TxD0 outputs the shift clock. 8 data bits are transmitted/ received (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. Mode 1: 8-bit UART, variable baud rate: 10 bits are transmitted (through TxD0) or received (through RxD0): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB80 in special function register S0CON. The baud rate is variable. Mode 2: 9-bit UART, fixed baud rate: 11 bits are transmitted (through TxD0) or received (through RxD0): a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). On transmission, the 9th data bit (TB80 in S0CON) can be assigned to the value of 0 or 1. For example, the parity bit (P in the PSW) could be moved into TB80 or a second stop bit by setting TB80 to 1. On reception the 9th data bit goes into RB80 in special function register S0CON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency.
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Mode 3: 9-bit UART, variable baud rate: 11 bits are transmitted (through TxD0) or received (through RxD0): a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). On transmission, the 9th data bit (TB80 in S0CON) can be assigned to the value of 0 or 1. For example, the parity bit (P in the PSW) could be moved into TB80 or a second stop bit by setting TB80 to 1. On reception, the 9th data bit goes into RB80 in special function register S0CON, while the stop bit is ignored. In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in mode 0 by the condition RI0 = 0 and REN0 = 1. Reception is initiated in the other modes by the incoming start bit if REN0 = 1. The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed. The corresponding interrupt request flags for serial interface 0 are TI0 or RI0, resp. See section 8 for more details about the interrupt structure. The interrupt request flags TI0 and RI0 can also be used for polling the serial interface 0 if the serial interrupt is not to be used (i.e. serial interrupt 0 not enabled). The control and status bits of the serial channel 0 in special function register S0CON are illustrated in figure 7-8. Figure 7-7 shows the special function register S0BUF which is the data register for receive and transmit. The following table summarizes the operating modes of serial interface 0.
Serial Interface 0, Mode Selection SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Descriptions Shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate
fOSC/12
Variable
fOSC/64 or fOSC/32
Variable
Figure 7-7 Special Function Register S0BUF (Address 99H) 99H Serial interface 0 buffer register S0BUF
Receive and transmit buffer of serial interface 0. Writing to S0BUF loads the transmit register and initiates transmission. Reading out S0BUF accesses a physically separate receive register.
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Figure 7-8 Special Function Register S0CON (Address 98H) 9FH 98H SM0 9EH SM1 9DH SM20 9CH REN0 9BH TB80 9AH RB80 99H TI0 98H RI0 S0CON
Bit SM0 0 0 1 1 SM20 SM1 0 1 0 1
Symbol Serial mode 0: Serial mode 1: Serial mode 2: Serial mode 3: Shift register mode, fixed baud rate 8-bit UART, variable baud rate 9-bit UART, fixed baud rate 9-bit UART, variable baud rate
Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3 and SM20 being set to 1, RI0 will not be activated if the received 9th data bit (RB80) is 0. In mode 1 and SM20 = 1, RI0 will not be activated if a valid stop bit has not been received. In mode 0, SM20 should be 0. Receiver enable. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. Transmitter bit 8. Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. Receiver bit 8. In modes 2 and 3 it is the 9th bit that was received. In mode 1, if SM20 = 0, RB80 is the stop bit that was received. In mode 0, RB80 is not used. Transmitter interrupt. Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must by cleared by software. Receiver interrupt. Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or during the stop bit time in the other modes, in any serial reception. Must be cleared by software.
REN0 TB80 RB80
TI0
RI0
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7.2.1.2 Multiprocessor Communication Feature Modes 2 and 3 of the serial interface 0 have a special provision for multi-processor communication. In these modes, 9 data bits are received. The 9th bit goes into RB80. Then a stop bit follows. The port can be programmed such that when the stop bit is received, the serial port 0 interrupt will be activated (i.e. the request flag RI0 is set) only if RB80 = 1. This feature is enabled by setting bit SM20 in S0CON. A way to use this feature in multiprocessor communications is as follows. lf the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM20 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM20 bit and prepare to receive the data bytes that will be coming. After having received a complete message, the slave sets SM20 again. The slaves that were not addressed leave their SM20 set and go on about their business, ignoring the incoming data bytes. SM20 has no effect in mode 0. In mode 1 SM20 can be used to check the validity of the stop bit. lf SM20 = 1 in mode 1, the receive interrupt will not be activated unless a valid stop bit is received. 7.2.1.3 Baud Rates of Serial Channel 0 As already mentioned there are several possibilities to generate the baud rate clock for the serial interface 0 depending on the mode in which it is operated. To clarify the terminology, something should be said about the difference between "baud rate clock" and "baud rate". The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization, as mentioned in the detailed description of the various operating modes in section 7.2.3. Therefore, the baud rate generators have to provide a "baud rate clock" to the serial interface which - there divided by 16 - results in the actual "baud rate". However, all formulas given in the following section already include the factor and calculate the final baud rate.
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Mode 0 The baud rate in mode 0 is fixed: Mode 0 baud rate = oscillator frequency 12
Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON (see figure 7-9). If SMOD = 0 (which is the value after reset), the baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency. Mode 2 baud rate = 2SMOD 64 x oscillator frequency
Figure 7-9 Special Function Register PCON (Address 87H)
87H SMOD
PDS
IDLS
SD
GF1
GF0
PDE
IDLE
PCON
These bits are not used in controlling serial interface 0.
Bit SMOD Modes 1 and 3
Function When set, the baud rate of serial interface 0 in modes 1, 2, 3 is doubled.
In these modes the baud rate is variable and can be generated alternatively by a dedicated baud rate generator or by timer 1. Using the baud rate generator: In modes 1 and 3, the SAB 80C517 can use the internal baud rate generator for serial interface 0. To enable this feature, bit BD (bit 7 of special function register ADCON0) must be set (see figure 7-10). This baud rate generator divides the oscillator frequency by 2496. Bit SMOD (PCON.7) also can be used to enable a multiply-by-two prescaler (see figure 7-9). At 12-MHz oscillator frequency, the commonly used baud rates 4800 baud (SMOD = 0) and 9600 baud (SMOD = 1) are available (with 0.16 % deviation). The baud rate is determined by SMOD and the oscillator frequency as follows:
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Mode 1, 3 baud rate =
2SMOD 2496
x oscillator frequency
Figure 7-10 Special Function Register ADCON0 (Address 0D8H) 0DFH 0D8H BD 0DEH CLK 0DDH ADEX 0DCH BSY 0DBH ADM 0DAH MX2 0D9H MX1 0D8H MX0 ADCON
These bits are not used in controlling serial interface 0.
Bit BD
Function Baud rate enable. When set, the baud rate in modes 1 and 3 of serial interface 0 is taken from a dedicated prescaler. Standard baud rates 4800 and 9600 baud at 12-MHz oscillator frequency can be achieved.
Using timer 1 to generate baud rates: In mode 1 and 3 of serial channel 0 timer 1 can be used for generating baud rates. Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows: Mode 1, 3 baud rate = 2SMOD 32 x (timer 1 overflow rate)
The timer 1 interrupt is usually disabled in this application. The timer itself can be configured for either "timer" or "counter" operation, and in any of its operating modes. In the most typical applications, it is configured for "timer" operation in the auto-reload mode (high nibble of TMOD = 0010B). In the case, the baud rate is given by the formula: Mode 1, 3 baud rate = 2SMOD x oscillator frequency 32 x 12 x (256 - (TH1))
One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as 16-bit timer (high nibble of TMOD = 0001B), and using the timer 1 interrupt for a 16-bit software reload. Table 7-4 lists various commonly used baud rates and shows how they can be obtained from timer 1.
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Table 7-4 Timer 1 Generated Commonly Used Baud Rates Baud Rate
fOSC (MHz)
SMOD C/T
Timer 1 Mode 2 2 2 2 2 2 2 1 Reload Value FFH FDH FDH FAH F4H E8H 72H FEEBH
Mode 1, 3:62.5 Kbaud 19.2 Kbaud 9.6 Kbaud 4.8 Kbaud 2.4 Kbaud 1.2 Kbaud 110 Baud 110 Baud
12.0 11.059 11.059 11.059 11.059 11.059 6.0 12.0
1 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Figure 7-11 shows the mechanisms for baud rate generation of serial channel 0, while table 7-5 summarizes the baud rate formulas for all usual configurations.
Figure 7-11 Generation of Baud Rates for Serial Channel 0
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Table 7-5 Baud Rates of Serial Interface 0 Baud Rate Derived from Timer 1 in mode 1 (see table 7-4) Interface Mode 1, 3 Baud Rate 2SMOD 2 1, 3 2SMOD 2 1 16 1 16 x (timer 1 overflow rate)
x
Timer 1 in mode 2 (see table 7-4)
x
x
fOSC
12 x (256 - (TH1))
Oscillator
2
2SMOD 2
x
1 16
x
fOSC
2
BD
1, 3
2SMOD 2
x
1 16
x
fOSC
1248
7.2.1.4 New Baud Rate Generator for Serial Channel 0 The SAB 80C517 devices with stepping code "CA" or later have a new baud rate generator for serial channel 0 which provides greater flexibility and better resolution. It substitutes the 80C517's baud rate generator at Serial Channel 0 which provides only 4.8 kBaud or 9.6 kBaud at 12 MHz crystal frequency. Since the new generator offers greater flexibility it is often possible to use it instead of Timer1 which is then free for other tasks. Figure 7-11a shows a block diagram of the new baud rate generator for Serial Channel 0. It consists of a free running 10-bit timer with fOSC /2 input frequency. On overflow of this timer there is an automatic reload from the registers S0RELL (address AAH) and S0RELH (address BAH). The lower 8 bits of the timer are reloaded from S0RELL, while the upper two bits are reloaded from bit 0 and 1 of register S0RELH. The baud rate timer is reloaded by writing to S0RELL.
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Figure 7-11a Baud Rate Generator for Serial Interface 0 The default value after reset of S0RELL is 0D9H, S0RELH contains XXXX XX11B Special Function Register S0RELH, S0RELL Bit No. MSB 7 LSB 0 S0RELH
6
5
4
3
2
1 msb
Addr. 0BAH
Bit No.
MSB 7
6
5
4
3
2
1
LSB 0 lsb S0RELL
Addr. 0AAH shaded areas are not used for programming the baudrate timer
Bit S0RELH.0-1 S0RELL.0-7
Function Reload value. Upper two bits of the timer reload value. Reload value. Lower 8 bit of timer reload value.
Reset value of S0RELL is 0D9H, S0RELH contains XXXX XX11B.
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Figure 7-11b shows a block diagram of the options available for baud rate generation of Serial Channel 0. It is a fully compatible superset of the functionality of older SAB 80C517 steppings. The new baud rate generator can be used in modes 1 and 3 of the Serial Channel 0. It is activated by setting bit BD (ADCON0.7). This also starts the baud rate timer. When Timer1 shall be used for baud rate generation, bit BD must be cleared. In any case, bit SMOD (PCON.7) selects an additional divider by two. The default values after reset in registers S0RELL and S0RELH provide a baud rate of 4.8 kBaud (with SMOD = 0) or 9.6 kBaud (with SMOD = 1) at 12 MHz oscillator frequency. This guarantees full compatibility to older steppings of the SAB 80C517.
Figure 7-11b Block Diagram of Baud Rate Generation for Serial Interface 0 If the new baud rate generator is used the baud rate of Serial Channel 0 in Mode 1 and 3 can be determined as follows: Mode 1, 3 baud rate = 2SMOD x oscillator frequency 64 x (210 - S0REL) with S0REL = S0RELH.1 - 0, S0RELL.7 - 0
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7.2.2
Serial Interface 1
7.2.2.1 Operating Modes of Serial Interface 1 The serial interface 1 is an asynchronous channel only and is able to operate in two modes, as an 8-bit or 9-bit UART. These modes, however, correspond to the above mentioned modes 1, 2 and 3 of serial interface 0. The multiprocessor communication feature is identical with this feature in serial interface 0. The serial interface 1 has its own interrupt request flags Rl1 and Tl1 which have a dedicated interrupt vector location (see section 8 for more details about the interrupts). The baud rate clock for this interface is generated by a dedicated baud rate generator. A more detailed description how to set the baud rate follows in section 7.2.2.3 and 7.2.2.4. Mode A: 9-bit UART, variable baud rate: 11 bits are transmitted (through TxD1) or received (through RxD1): a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). On transmission, the 9th data bit (TB81 in S1CON) can be assigned to the value of 0 or 1. For example, the parity bit (P in the PSW) could be moved into TB81 or a second stop bit by setting TB81 to 1. On reception the 9th data bit goes into RB81 in special function register S0CON, while the stop bit is ignored. In fact, mode A of serial interface 1 is identical with mode 2 or 3 of serial interface 0 in all respects except the baud rate generation (see section 7.2.2.3). Mode B: 8-bit UART, variable baud rate: 10 bits are transmitted (through TxD1) or received (through RxD1): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB81 in special function register S1CON. In fact, mode B of serial interface 1 is identical with mode 1 of serial interface 0 in all respects except for the baud rate generation (see section 7.2.2.3). In both modes, transmission is initiated by any instruction that uses S1BUF as a destination register. Reception is initiated by the incoming start bit if REN1 = 1. The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed. The corresponding interrupt request flags for serial interface 1 are Tl1 or Rl1, resp. See section 8 for more details about the interrupt structure. The interrupt request flags Tl1 and Rl1 can also be used for polling the serial interface 1 if the serial interrupt shall not be used (i.e. serial interrupt 1 not enabled). The control and status bits of the serial channel 1 in special function register S1CON are illustrated in figure 7-12. Figure 7-13 shows the special function register S1BUF which is the data register for receive and transmit. Note that these special function registers are not bit-addressable. Due to this fact bit instructions cannot be used for manipulating these registers. This is important especially for S1CON where a polling and resetting of the Rl1 or Tl1 request flag cannot be performed by JNB and CLR instructions but must be done by a sequence of byte instructions, e.g.: LOOP: MOV JNB ANL A,S1CON ACC.0,LOOP S1CON,#0FEH ;Testing of RI1 ;Resetting of RI1
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Figure 7-12 Special Function Register S1CON (Address 9BH) 9BH SM - SM21 REN1 TB81 RB81 TI1 RI1 S1CON
Bit SM SM21
Function SM = 0: serial mode A; 9-bit UART SM = 1: serial mode B; 8-bit UART Enables the multiprocessor communication feature in mode A. If SM21 is set to 1, RI1 will not be activated if the received 9th data bit (RB81) is 0. In mode B, if SM21 = 1, RI1 will not be activated if a valid stop bit was not received. Receiver enable of interface 1. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. Transmitter bit 8 of interface 1. Is the 9th data bit that will be transmitted in mode A. Set or cleared by software as desired. Receiver bit 8 of interface 1. Is the 9th data bit that was received in mode A. In mode B, if SM21 = 0, RB81 is the stop bit that was received. Transmitter interrupt of interface 1. Is the transmit interrupt flag. Set by hardware at the beginning of the stop bit in any serial transmission. Must be cleared by software. Receiver interrupt of interface 1. Is the receive interrupt flag. Set by hardware at the halfway through the stop bit time in any serial reception. Must be cleared by software.
REN1
TB81 RB81 TI1
RI1
Figure 7-13 Special Function Register S1BUF (Address 9CH) 9CH Serial interface 1 buffer register S1BUF
Receive and transmit buffer of serial interface 1. Writing to S1BUF loads the transmit register and initiates transmission. Reading out S1BUF accesses a physically separate receive register.
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7.2.2.2 Multiprocessor Communication Feature Mode A of the serial interface 1 has a special provision for multiprocessor communication. In this mode, 9 data bits are received. The 9th bit goes into RB81. Then follows a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt (i.e. the request flag Rl1 is set) will be activated only if RB81 = 1. This feature is enabled by setting bit SM21 in S1CON. A way to use this feature in multiprocessor communications is as follows. lf the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM21 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM21 bit and prepare to receive the data bytes that will be coming. After having received a complete message, the slave is setting SM21 again. The slaves that were not addressed leave their SM21 set and go on about their business, ignoring the incoming data bytes. In mode B SM21 can be used to check the validity of the stop bit. lf SM21 = 1 in mode B, the receive interrupt will not be activated unless a valid stop bit is received. 7.2.2.3 Baud Rates of Serial Channel 1 As already mentioned serial interface 1 uses its own dedicated baud rate generator for baud rate generation in both operating modes (see figure 7-14). This baud rate generator consists of a free running 8-bit timer with fOSC/2 input frequency. The timer is automatically reloaded at overflow by the contents of register S1REL (see figure 7-15). The timer must be started by writing the desired reload value to register S1REL. The baud rate in operating modes A and B can be determined by following formula: oscillator frequency Mode A, B baud rate = 32 x (256 - S1REL) At 12-MHz oscillator frequency a baud rate range from about 1.5 kbaud up to 375 kbaud is covered. Using the fast baud rates offers the same functionality as the operating mode 2 in serial interface 0 with its fixed baud rates.
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Figure 7-14 Baud Rate Generator for Serial Interface 1 Figure 7-15 Special Function Register S1REL (Address 9DH) 9DH Serial interface 1 reload register S1REL
8-bit reload register for baud rate generator of serial interface 1. 7.2.2.4 New Baud Rate Generator for Serial Channel 1 A new baud rate generator for Serial Channel 1, which is implemented in SAB 80C517 devices with stepping code "CA" or later, now offers a wider range of selectable baud rates. Especially a baud rate of 1200 baud can be achieved now. The baud rate generator itself is identical with the one used for Serial Channel 0. It consists of a free running 10-bit timer with FOSC /2 input frequency. On overflow of this timer there is an automatic reload from the registers S1REL (address 9DH) and S1RELH (address BBH). The lower 8 bits of the timer are reloaded from S0REL, while the upper two bits are reloaded from bit 0 and 1 of register S1RELH. The baud rate timer is reloaded by writing to S1REL. The baud rate in Mode A and B can be determined by the following formula: Mode A, B baud rate = oscillator frequency 32 x (210 - Reload Value)
with Reload Value = S1RELH.1 - 0, S1RELL.7 - 0
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Figure 7-15A shows a block diagram of the baud rate generator for Serial Interface 1.
Figure 7-15A Baud Rate Generator for Serial Interface 1 Special Function Register S1RELH, S1RELL Bit No. MSB 7 Addr. 0BBH 6 5 4 3 2 1 msb LSB 0 S1RELH
Bit No.
MSB 7 6 5 4 3 2 1
LSB 0 lsb S1REL
Addr. 09DH shaded areas are not used for programming the baudrate timer
Bit S1RELH.0-1 S1REL.0-7
Function Reload value. Upper two bits of the timer reload value. Reload value. Lower 8 bit of timer reload value.
Reset value of S1REL is 00H, S1RELH contains XXXX XX11B. Semiconductor Group 65
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7.2.3
Detailed Description of the Operating Modes
The following sections give a more detailed description of the several operating modes of the two serial interfaces. The sections 7.2.3.2. and 7.4.3.4. apply to both of the serial interfaces. The description of the synchronous mode 0 and the asynchronous mode 2 refers only to serial interface 0. 7.2.3.1 Mode 0, Synchronous Mode (Serial Interface 0) Serial data enters and exits through RxD0. TxD0 outputs the shift clock. 8 bits are transmitted/ received: 8 data bits (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. Figures 7-16 a) and b) show a simplified functional diagram of the serial port in mode 0, and associated timing. Transmission is initiated by any instruction that uses S0BUF as a destination register. The "writeto-S0BUF" signal at S6P2 also loads a 1 into the 9th bit position of the transmit shift register and tells the TX control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write-to-S0BUF" and activation of SEND. SEND enables the output of the shift register to the alternate output function line P3.0, and also enables SHIFT CLOCK to the alternate output function line P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2, while the interface is transmitting. Before and after transmission SHIFT CLOCK remains high. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register is shifted one position to the right. As data bits shift to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX control block to do one last shift and then deactivates SEND and sets TI0. Both of these actions occur at S1P1 in the 10th machine cycle after "write-to-S0BUF". Reception is initiated by the condition REN0 = 1 and RI0 = 0. At S6P2 in the next machine cycle, the RX control unit writes the bits 1111 1110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 in every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted one position to the left. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 in the same machine cycle. As data bits come in from the right, 1 s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX control block to do one last shift and load S0BUF. At S1P1 in the 10th machine cycle after the write to S0CON that cleared RI0, RECEIVE is cleared and RI0 is set.
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7.2.3.2 Mode 1/Mode B, 8-Bit UART (Serial Interfaces 0 and 1) Ten bits are transmitted (through TxD0 or TxD1), or received (through RxD0 or RxD1): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception through RxD0, the stop bit goes into RB80 (S0CON), on reception through RxD1, RB81 (S1C0N) stores the stop bit. The baud rate for serial interface 0 is determined by the timer 1 overflow rate or by the internal baud rate generator of serial interface 0. Serial interface 1 receives the baud rate clock from its own baud rate generator. Figures 7-17 a) and b) show a simplified functional diagram of both serial channels in mode 1 or mode B, resp. The generation of the baud rate clock by the various timers is described in sections 7.2.1.3 and 7.2.2.3. Transmission is initiated by any instruction that uses S0BUF/S1BUF as a destination register. The "write-to-S0BUF/S1BUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control block that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next roll-over in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-S0BUF/S1BUF" signal). The transmission begins with activation of SEND, which puts the start bit to TxD0/TxD1. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD0/ TxD1. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just left of the MSB, and all positions to the left of that contain zero. This condition flags the TX control to do one last shift and then deactivate SEND and set TI0/Tl1. This occurs at the 10th divideby-16 rollover after "write-to-S0BUF/S1BUF". Reception is initiated by a detected 1-to-0 transition at RxD0/RxD1. For this purpose RxD0/RxD1 is sampled at a rate of 16 times whatever baud rate has been established. When a reception is detected, the divide-by-16 counter is immediately reset, and 1 FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollover with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16 counter states. At the 7th, 8th and 9th counter state of each bit time, the bit detector samples the value of RxD0/RxD1. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. lf the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. This is to provide rejection of false start bits. lf the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come from the right, 1's shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1/B is a 9-bit register), it flags the RX control block to do one last shift. The signal to load S0BUF/S1BUF and RB80/RB81, and to set RI0/Rl1 will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) 2) RI0/Rl1 = 0, and either SM20/SM21 = 0 or the received stop bit = 1
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lf either of these two conditions is not met the received frame is irretrievably lost. lf both conditions are met, the stop bit goes into RB80/RB81, the 8 data bits go into S0BUF/S1BUF, and RI0/Rl1 is activated. At this time, no matter whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD0/RxD1. 7.2.3.3 Mode 2, 9-Bit UART (Serial Interface 0) Mode 2 is functionally identical to mode 3 (see below). The only exception is, that in mode 2 the baud rate can be programmed to two fixed quantities: either 1/32 or 1/64 of the oscillator frequency. Note that serial interface 0 cannot achieve this baud rate in mode 3. Its baud rate clock is generated by timer 1, which is incremented by a rate of fOSC/12. The dedicated baud rate generator of serial interface 1 however is clocked by a fOSC/2-signal and so its maximum baud rate is fOSC/32. 7.2.3.4 Mode 3 / Mode A, 9-Bit UART (Serial Interfaces 0 and 1) Eleven bits are transmitted (through TxD0/TxD1), or received (through RxD0/RxD1): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB80/TB81) can be assigned the value of 0 or 1. On reception the 9th data bit goes into RB80/ RB81 in S0CON/S1CON. Figures 7-18 a) and b) show a functional diagram of the serial interfaces in mode 2 and 3 or mode A, resp. and associated timing. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses S0BUF/S1BUF as a destination register. The "write to S0BUF/S1BUF" signal also loads TB80/TB81 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus the bit times are synchronized to the divide-by-16 counter, and not to the "write-to-S0BUF/S1BUF" signal). The transmission begins with the activation of SEND, which puts the start bit to TxD0/TxD1. One bit time later, DATA is activated which enables the output bit of transmit shift register to TxD0/TxD1. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data shift out to the right, zeros are clocked in from the left. When TB80/TB81 is at the output position of the shift register, then the stop bit is just left of the TB80/TB81, and all positions to the left of that contain zeros.
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This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI0/ TI1. This occurs at the 11th divide-by-16 rollover after "write-to-S0BUF/S1BUF". Reception is initiated by a detected 1-to-0 transition at RxD0/RxD1. For this purpose RxD0/RxD1 is sampled of a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FH is written to the input shift register. At the 7th, 8th and 9th counter state of each bit time, the bit detector samples the value of RxD0/ RxD1. The value accepted is the value that was seen in at least 2 of the 3 samples. lf the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. lf the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come from the right, 1's shift out to the left. When the start bit arrives at the leftmost position in the shift register (which is a 9-bit register), it flags the RX control block to do one last shift, load S0BUF/S1BUF and RB80/ RB81, and set RI0/RI1. The signal to load S0BUF/S1BUF and RB80/RB81, and to set RI0/RI1, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) RI0/RI1 = 0, and 2) either SM20/SM21 = 0 or the received 9th data bit = 1 lf either one of these two conditions is not met, the received frame is irretrievably lost, and RI0/Rl1 is not set. lf both conditions are met, the received 9th data bit goes into RB80/RB81, the first 8 data bits go into S0BUF/S1BUF. One bit time later, no matter whether the above conditions are met or not, the unit goes back to look for a 1-to-0 transition at the RxD0/RxD1 input. Note that the value of the received stop bit is irrelevant to S0BUF/S1BUF, RB80/RB81, or RI0/Rl1.
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Figure 7-16 a) Functional Diagram - Serial Interface 0, Mode 0
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Figure 7-16 b) Timing Diagram - Serial Interface 0, Mode 0
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Figure 7-17 a) Functional Diagram - Serial Interfaces 0 and 1, Mode 1 / Mode B Semiconductor Group 72
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Figure 7-17 b) Timing Diagram - Serial Interfaces 0 and 1, Mode 1 / Mode B
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Figure 7-18 a) Functional Diagram - Serial Interfaces 0 and 1, Modes 2 and 3 / Mode A
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Figure 7-18 b) Timing Diagram - Serial Interfaces 0 and 1, Modes 2 and 3 / Mode A
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7.3
Timer 0 and Timer 1
The SAB 80C517 has a number of general purpose 16-bit timer/counters: timer 0, timer 1, timer 2 and the compare timer (timer 2 and the compare timer are discussed separately in section 7.5 "Compare/Capture Unit"). Timer/counter 0 and 1 are fully compatible with timer/counters 0 and 1 of the SAB 8051 and can be used in the same operating modes. Timer/counter 0 and 1 which are discussed in this section can be configured to operate either as timers or event counters: - In "timer" function, the register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. - In "counter" function, the register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5, resp.). In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. In addition to the "timer" and "counter" selection, timer/counters 0 and 1 have four operating modes from which to select.
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Figure 7-19 Special Function Register TCON (Address 88H) 8FH 88H TF1 8EH TR1 8DH TF0 8CH TR0 8BH IE1 8AH IT1 89H IE0 88H IT0 TCON
These bits are not used in controlling timer/counter 0 and 1.
Bit TR0 TF0 TR1 TF1
Function Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 ON/OFF. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 ON/OFF. Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine.
Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD, shown in figures 7-19 and 7-20. In the following descriptions the symbols TH0 and TL0 are used specify the high-byte and low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicitly noted, this applies also to timer 1.
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Figure 7-20 Special Function Register TMOD (Address 89H)
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
TMOD
Timer 1 Timer/counter 0/1 mode control register
Timer 0
Bit Gate
Symbol Gating control. When set, timer/counter "x" is enabled only while "INTx" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set. Counter or timer select bit. Set for counter operation (input from "Tx" input pin). Cleared for timer operation (input from internal system clock). M0 0 8-bit timer/counter "THx" operates as 8-bit timer/counter "TLx" serves as 5-bit prescaler. 16-bit timer/counter. "THx" and "TLx" are cascaded; there is no prescaler. 8-bit auto-reload timer/counter. "THx" holds a value which is to be reloaded into "TLx" each time it overflows. Timer 0: TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH00 is an 8-bit timer only controlled by timer 1 control bits. Timer 1: Timer/counter 1 stops
C/T
M1 0
0 1
1 0
1
1
1
1
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7.3.1
Mode 0
Putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 7-21 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1's to all 0's, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt (see section 8 for details about the interrupt structure). The counted input is enabled to the timer when TR0 = 1 and either GATE = 0 or INT0 = 1 (setting GATE = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR1, TF1, TH1, TL1, and INT1 for the corresponding timer 1 signals in figure 7-21. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3).
Figure 7-21 Timer/Counter 0/1, Mode 0: 13 Bit Timer/Counter Semiconductor Group 79
On-Chip Peripheral Components
7.3.2
Mode 1
Mode 1 is the same as mode 0, except that the timer register is run with all 16 bits. Mode 1 is shown in figure 7-22.
Figure 7-22 Timer/Counter 0/1, Mode 1: 16-Bit Timer/Counter
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7.3.3
Mode 2
Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 7-23. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.
Figure 7-23 Timer/Counter 0/1, Mode 2: 8-Bit Timer/Counter with Auto-Reload
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7.3.4
Mode 3
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3 on timer 0 is shown in figure 7-24. TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself.
Figure 7-24 Timer/Counter 0, Mode 3: Two 8-Bit Timer/Counter
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7.4
A/D Converter
The SAB 80C517 provides an A/D converter with the following features: - - - - - - 12 multiplexed input channels, which can also be used as digital inputs (port 7, port 8) Programmable internal reference voltages (16 steps each) via resistor array 8-bit resolution within the selected reference voltage range 13 microseconds conversion time (including sample time) at 12-MHz oscillator frequency Selectable external or internal start-of-conversion trigger Interrupt request generation after each conversion
For the conversion, the method of successive approximation via capacitor array is used. The externally applied reference voltage range has to be held on a fixed value within the specifications (see section "A/D Converter Characteristics" in the data sheet). The internal reference voltages can be varied to reduce the reference voltage range of the A/D converter and thus to achieve a higher resolution. Figure 7-25 shows a block diagram of the A/D converter. There are four user-accessible special function registers: ADCON0, ADCON1 (A/D converter control registers), ADDAT (A/D converter data register) and DAPR (D/A converter program register) for the programmable reference voltages. The analog input channels (port 7 and port 8) can also be used for digital input; refer also to section 7.1 "Parallel I/O". 7.4.1 Function and Control
7.4.1.1 lnitialization and Input Channel Selection Special function register ADCON0 which is illustrated in figure 7-26 is used to set the operating modes, to check the status, and to select one of eight analog input channels. Special function register ADCON1 (figure 7-27) controls the selection of all twelve input channels. Register ADCON0 contains two mode bits. Bit ADM is used to choose the single or continuous conversion mode. In single conversion mode only one conversion is performed after starting, while in continuous conversion mode after the first start a new conversion is automatically started on completion of the previous one.
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Figure 7-25 Block Diagram of the A/D Converter
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An externally controlled conversion can be achieved by setting the bit ADEX. In this mode on single conversion is triggered by a 1-to-0 transition at pin P6.0/ADST, if ADM is 0. P6.0/ADST is sampled suring S5P2 of every machine cycle. When the samples show a logic high in one cycle and a logic low in the next cycle the transition is detected and the conversion is started. When ADM and ADEX is set, a continuous conversion is started when pin P6.0/ADST sees a low level; the conversion is stopped when the pin P6.0/ADST goes back to high. The last commenced conversion during low level will be completed. The busy flag BSY (ADCON0.4) is automatically set when a conversion is in progress. After completion of the conversion it is reset by hardware. This flag can be read only, a write has no effect.There is also an interrupt request flag IADC (IRCON.0) that is set when a conversion is completed. See section 8 for more details about the interrupt structure.
Figure 7-26 Special Function Register ADCON0 (Address 0D8H) 0DFH 0D8H BD 0DEH CLK 0DDH ADEX 0DCH BSY 0DBH ADM 0DAH MX2 0D9H MX1 0D8H MX0 ADCON0
These bits are not used in controlling A/D converter functions.
Bit MX0 MX1 MX2 MX3 ADM BSY
Function Select 12 input channels of the A/D converter.
A/D conversion mode. When set, a continuous conversion is selected. If ADM = 0, the converter stops after one conversion. Busy flag. This flag indicates whether a conversion is in progress (BSY = 1). The flag is cleared by hardware when the conversion is completed. Internal/external start of conversion. When set, the external start of conversion by P6.0/ADST is enabled.
ADEX
Figure 7-27 Special Function RegisterADCON1 (Address 0DCH) 0DCH - - - - MX3 MX2 MX1 MX0 ACON1
A/D converter control register 1. It contains channel selection bits MX0 to MX3. Bits MX0 to MX2 can be written or read either in ADCON0 or in ADCON1.
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Table 7-6 Selection of the Analog Input Channels MX3 0 0 0 0 0 0 0 0 1 1 1 1 MX2 0 0 0 0 1 1 1 1
X
*)
MX1 0 0 1 1 0 0 1 1 0 0 1 1
MX0 0 1 0 1 0 1 0 1 0 1 0 1
Selected Channel Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Analog input 8 Analog input 9 Analog input 10 Analog input 11
Pin P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P8.0 P8.1 P8.2 P8.3
X X X
*) X means that the value may be 1 or 0.
The bits MX0 to MX2 in special function register ADCON0 and the bits MX0 to MX3 in ADCON1 are used for selection of the analog input channel. Table 7-6 lists the selected input channels. The bits MX0 to MX2 are represented in both the registers ADCON0 and ADCON1; however, these bits are present only once; it has the same effect irrespective of whether they are accessed via ADCON0 or ADCON1. This is done in order to maintain software compatibility to the SAB 80(C)515. In this device there are only eight input channels which are selected by MX0 to MX2 in ADCON0. Thus, a program written for the SAB 80(C)515 selects one of the lower eight input channels (port 7) if the bit MX3 is reset which is the default value after reset. (For clarity: In the SAB 80(C)515 the analog input channel is called port 6 or AN0 to AN7, resp. However, it is found on the same address (0DB H) as the SAB 80C517's port 7.) lf all 12 multiplexed input channels are required register ADCON1 is to be used. lt contains a fourbit field to select one of all 12 input channels, the eight inputs at port 7 and the four inputs at port 8. Thus, there are two methods of selecting a channel of port 7 and it does not matter which is used: if a new channel is selected in ADCON1 the change is automatically done in the corresponding bits MX0 to MX2 in ADCON0 and vice versa. lf bit MX3 is set, the additional analog inputs at port 8 are used. MX0 and MX1 then determine which channel of port 8 is being selected (see table 7-6).
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Ports P7 and P8 are dual purpose input ports. lf the input voltage meets the specified logic levels, they can be used as digital inputs as well regardless of whether the pin levels are sampled by the A/D converter at the same time. The special function register ADDAT (figure 7-28) holds the converted digital 8-bit data result. The data remains in ADDAT until it is overwritten by the next converted data. ADDAT can be read or written under software control. lf the A/D converter of the SAB 80C517 is not used, register ADDAT can be used as an additional general purpose register.
Figure 7-28 Special Function Register ADDAT (Address 0D9H) 0D9H Conversion result ADDAT
This register contains the 8-bit conversion result. 7.4.1.2 Start of Conversion An internal start of conversion (ADEX = 0) is triggered by a write-to-DAPR instruction. The start procedure itself is independent of the value which is written to DAPR. However, the value in DAPR determines which internal reference voltages are used for the conversion (see section 7.4.2). When single conversion mode is selected (ADM = 0) only one conversion is performed. In continuous mode after completion of a conversion a new conversion is triggered automatically, until bit ADM is reset. When external start of conversion is selected a write-to-DAPR will not start the conversion; in this case, conversion starts when a falling edge at pin P6.0/ADST is detected. In single conversion mode one conversion is performed until the next falling edge at P6.0/ADST is recognized. In continuous mode new conversions are started automatically as long as pin P6.0/ADST is on low level. This is done until P6.0/ADST goes to logic high level; in this case the last commenced conversion is completed. 7.4.2 Reference Voltages
The SAB 80C517 has two pins to which a reference voltage range for the on-chip A/D converter is applied (pin V AREF for the upper voltage and pin V AGND for the lower voltage). In contrast to conventional A/D converters it is now possible to use not only these externally applied reference voltages for the conversion but also internally generated reference voltages which are derived from the externally applied ones. For this purpose a resistor ladder provides 16 equidistant voltage levels between VAREF and VAGND. These steps can individually be assigned as upper and lower reference voltage for the converter itself. These internally generated reference voltages are called VlNTAREF and VlNTAGND. The internal reference voltage programming can be thought of as a programmable "D/A converter" which provides the voltages VINTAREF and VINTAGND for the A/D converter itself.
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The SFR DAPR (see figure 7-29) is provided for programming the internal reference voltages VINTAREF and VlNTAGND. For this purpose the internal reference voltages can be programmed in steps of 1/16 of the external reference voltages (VAREF - VAGND) by four bits each in register DAPR. Bits 0 to 3 specify VlNTAGND, while bits 4 to 7 specify VINTAREF. A minimum of 1 V difference is required between the internal reference voltages VlNTAREF and VINTAGND for proper operation of the A/D converter. This means, for example, in the case where VAREF is 5 V and VAGND is 0 V, there must be at least four steps difference between the internal reference voltages VINTAREF and VINTAGND. The values of VIntAGND and VIntAREF are given by the formulas: DAPR (.3-.0) 16
VINTAGND = VAGND +
(VAREF - VAGND)
with DAPR (.3-.0) < CH;
VINTAREF = VAGND +
DAPR (.7-.4)
16 with DAPR (.7-.4) > 3H;
(VAREF - VAGND)
DAPR (.3-.0) is the contents of the low-order nibble, and DAPR (.7-.4) the contents of the high-order nibble of DAPR.
Figure 7-29 Special Function Register DAPR (Address DAH) 0DAH Programming of VINTAREF Programming of VINTAGND DAPR
D/A converter program register. Each 4-bit nibble is used to program the internal reference voltages. Write-access to DAPR starts conversion. DAPR (.3-.0) 16
VINTAGND = VAGND +
(VAREF - VAGND)
with DAPR (.3-.0) < 13;
VINTAREF = VAGND +
DAPR (.7-.4) 16
(VAREF - VAGND)
with DAPR (.7-.4) > 3;
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If DAPR (.3-.0) or DAPR (.7-.4) = 0, the internal reference voltages correspond to the external reference voltages VAGND and VAREF, respectively. If VAINPUT > VINTAREF, the conversion result is 0FFH, if VAINPUT < VINTAGND , the conversion result is 00H (VAINPUT is the analog input voltage). If the external reference voltages VAGND = 0 V and VAREF = + 5 V (with respect to VSS and VCC) are applied, then the following internal reference voltages VINTAGND and VINTAREF shown in table 7-7 can be adjusted via the special function register DAPR. Table 7-7 Adjustable Internal Reference Voltages Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DAPR (.3-.0) DAPR (.7-.4) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
VINTAGND
0.0 0.3125 0.625 0.9375 1.25 1.5625 1.875 2.1875 2.5 2.8125 3.125 3.4375 3.75 - - -
VINTAREF
5.0 - - - 1.25 1.5625 1.875 2.1875 2.5 2.8125 3.125 3.4375 3.75 4.0625 4.375 4.6875
The programmability of the internal reference voltages allows adjusting the internal voltage range to the range of the external analog input voltage or it may be used to increase the resolution of the converted analog input voltage by starting a second conversion with a compressed internal reference voltage range close to the previously measured analog value. Figures 7-30 and 7-31 illustrate these applications.
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Figure 7-30 Adjusting the Internal Reference Voltages to the Range of the External Analog Input Voltages
Figure 7-31 Increasing the Resolution by a Second Conversion
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The external reference voltage supply need only be applied when the A/D converter is used, otherwise the pins VAREF and VAGND may be left unconnected. The reference voltage supply has to meet some requirements concerning the level of VAGND and VAREF and the output impedance of the supply voltage (see also "A/D Converter Characteristics" in the data sheet). - The voltage VAREF must meet the following specification: VAREF = VCC +/- 5 % - The voltage VAGND must meet a similar specification: VAGND = VSS + /- 0.2 V - The differential output impedance of the analog reference supply voltage should be less than 1 k. lf the above mentioned operating conditions are not met the accuracy of the converter may be decreased. Furthermore, the analog input voltage VAINPUT must not exceed the range from (VAGND - 0.2 V) to (VAREF + 0.2 V). Otherwise, a static input current might result at the corresponding analog input which will also affect the accuracy of the other input channels. 7.4.3 A/D Converter Timing
A conversion is internally started by writing into special function register DAPR (ADEX = 0). A writeto-DAPR will start a new conversion even if a conversion is currently in progress. The conversion begins with the next machine cycle and the busy flag BSY will be set. When external start is selected (ADEX = 1) the conversion starts in the machine cycle following the one where the low level was detected at P6.0/ADST. The conversion procedure is divided into three parts: Load time (tL): During this time the analog input capacitance CI (see data sheet) must be loaded to the analog input voltage level. The external analog source needs to be strong enough to source the current to load the analog input capacitance during the load time. This causes some restrictions for the impedance of the analog source. Sample time (tS): During this time the internal capacitor array is connected to the selected analog input channel. The sample time includes the load time which is described above. After the load time has passed the selected analog input must be held constant for the rest of the sample time. Otherwise the internal calibration of the comparator circuitry could be affected which might result in a reduced accuracy of the converter. However, in typical applications a voltage change of approx. 200 - 300 mV at the inputs during this time has no effect.
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Conversion time (tC): The conversion time tC includes the sample and load time. Thus, tC is the total time required for one conversion. After the load time and sample time have elapsed, the conversion itself is performed during the rest of tC. In the last machine cycle the converted result is moved to ADDAT; the busy flag (BSY) is cleared before. The A/D converter interrupt is generated by bit IADC in register IRCON. IADC is already set some cycles before the result is written to ADDAT. The flag IADC is set before the result is available in ADDAT because the shortest possible interrupt latency time is taken into account in order to ensure optimal performance. Thus, the converted result appears at the same time in ADDAT when the first instruction of the interrupt service routine is executed. Similar considerations apply to the timing of the flag BSY where usually a "JB BSY,$" instruction is used for polling. lf a continuous conversion is established, the next conversion is automatically started in the machine cycle following the last cycle of the previous conversion.
Figure 7-32 Timing Diagram of an A/D Converter
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7.5
The Compare/Capture Unit (CCU)
The compare/capture unit is one of the SAB 80C517's most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. The CCU consists of two 16-bit timer/counters with automatic reload feature and an array of 13 compare or compare/capture registers. A set of six control registers is used for flexible adapting of the CCU to a wide variety of user's applications. The CCU is the ideal peripheral for various automotive control applications (ignition/injection control, anti-lock brakes, etc.) as well as for industrial applications (DC, three-phase AC, and stepper motor control, frequency generation, digital-to-analog conversion, process control, etc.) The detailed description in the following sections refers to the CCU's functional blocks as listed below: - Timer 2 with fOSC/12 input clock, 2-bit prescaler, (4-bit prescaler, in SAB 80C517 identification mark "BB" or later), 16-bit reload, counter/gated timer mode and overflow interrupt request. - Compare timer with fOSC/2 input clock, 8-bit prescaler, 16-bit reload and overflow interrupt request. - Compare/(reload/)capture register array consisting of four different kinds of registers: one 16-bit compare/reload/capture register, three 16-bit compare/capture registers, one 16-bit compare/capture register with additional "concurrent compare" feature, eight 16-bit compare registers with timer-overflow controlled loading. Altogether the register array may control up to 21 output lines and can request up to 7 independent interrupts. For brevity, in the following text all double-byte compare, compare/capture or compare/reload/ capture registers are called CMx (x = 0 ... 7), CCx (x = 0 ... 4) or CRC register, respectively. The block diagram in figure 7-33 shows the general configuration of the CCU. All CCx registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to provide up to 8 PWM channels. The assignment of the CMx registers - which can be done individually for every single register - is combined with an automatic selection of one of the two possible compare modes.
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Port 5, port 4 and seven lines of port 1 have alternate functions dedicated to the CCU. These functions are listed in table 7-8. Normally each register controls one dedicated output line at the ports. Register CC4 is an exception as it can manipulate up to nine output lines (one at port 1.4 and the other eight at port 5) concurrently. This feature, the "concurrent compare", is described in section 7.5.5.1. Note that for an alternate input function the port-bit latch has to be programmed with a '1'. For bit latches of port pins that are used as compare outputs, the value to be written to the bit latches depends on the compare mode established. A list of all special function registers concerned with the CCU is given in table 7-9.
Figure 7-33 Block Diagram of the CCU Semiconductor Group 94
On-Chip Peripheral Components
Table 7-8 Alternate Port Functions of the CCU Pin Symbol P5.0/CCM0 P5.1/CCM1 P5.2/CCM2 P5.3/CCM3 P5.4/CCM4 P5.5/CCM5 P5.6/CCM6 P5.7/CCM7 P4.7/CM7 P4.6/CM6 P4.5/CM5 P4.4/CM4 P4.3/CM3 P4.2/CM2 P4.1/CM1 P4.0/CM0 P1.7/T2 P1.5/T2EX P1.4/INT2/CC4 P1.3/INT6/CC3 P1.2/INT5/CC2 P1.1/INT4/CC1 P1.0/INT3/CC0 Pin
No.1)
Alternate Function Concurrent compare 0 Concurrent compare 1 Concurrent compare 2 Concurrent compare 3 Concurrent compare 4 Concurrent compare 5 Concurrent compare 6 Concurrent compare 7 Comp. output for the CM7 reg. Comp. output for the CM6 reg. Comp. output for the CM5 reg. Comp. output for the CM4 reg. Comp. output for the CM3 reg. Comp. output for the CM2 reg. Comp. output for the CM1 reg. Comp. output for the CM0 reg. External count or gate input to timer 2 External reload trigger input Comp. output/capture input for CC register 4 Comp. output/capture input for CC register 3 Comp. output/capture input for CC register 2 Comp. output/capture input for CC register 1 Comp. output/capture input for CRC register
68 67 66 65 64 63 62 61 9 8 7 6 5 3 2 1 29 31 32 33 34 35 36
1) Pin numbering refers to the P-LCC-84 package
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Table 7-9 Special Function Registers of the CCU Symbol CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL CTCON CTRELH CTRELL IRCON TH2 TL2 T2CON Description Comp./capture enable reg. Comp./capture 4 enable reg. Comp./capture reg. 1, high byte Comp./capture reg. 2, high byte Comp./capture reg. 3, high byte Comp./capture reg. 4, high byte Comp./capture reg. 1, low byte Comp./capture reg. 2, low byte Comp./capture reg. 3, low byte Comp./capture reg. 4, low byte Compare enable register Compare reg. 0, high byte Compare reg. 1, high byte Compare reg. 2, high byte Compare reg. 3, high byte Compare reg. 4, high byte Compare reg. 5, high byte Compare reg. 6, high byte Compare reg. 7, high byte Compare reg. 0, low byte Compare reg. 1, low byte Compare reg. 2, low byte Compare reg. 3, low byte Compare reg. 4, low byte Compare reg. 5, low byte Compare reg. 6, low byte Compare reg. 7, low byte Compare input select Com./rel./capt. reg., high byte Com./rel./capt. reg., low byte Com. timer control reg. Com. timer rel. reg., high byte Com. timer rel. reg., low byte Interrupt control register Timer 2, high byte Timer 2, low byte Timer 2 control register Address 0C1H 0C9H 0C3H 0C5H 0C7H 0CFH 0C2H 0C4H 0C6H 0CEH 0F6H 0D3H 0D5H 0D7H 0E3H 0E5H 0E7H 0F3H 0F5H 0D2H 0D4H 0D6H 0E2H 0E4H 0E6H 0F2H 0F4H 0F7H 0CBH 0CAH 0E1H 0DFH 0DEH 0C0H 0CDH 0CCH 0C8H
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7.5.1
Timer 2
Timer 2 is one of the two 16-bit time bases of the compare/capture unit. It can operate as timer, event counter, or gated timer. The block diagram in figure 7-34 a) shows the general configuration of the timer 2.
Figure 7-34 a) Block Diagram of Timer 2
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Timer Mode In timer function, the count rate is derived from the oscillator frequency. A 2:1 prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. Thus, the 16-bit timer register (consisting of TH2 and TL2) is either incremented in every machine cycle or in every second machine cycle. The prescaler is selected by bit T2PS in special function register T2CON (see figure 7-35). lf T2PS is cleared, the input frequency is 1/12 of the oscillator frequency; if T2PS is set, the 2:1 prescaler gates 1/24 of the oscillator frequency to the timer. Gated Timer Mode In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This will facilitate pulse width measurements. The external gate signal is sampled once every machine cycle (for the exact port timing, please refer to section 7.1 "Parallel I/O"). Event Counter Mode In the counter function, the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. When the sampled inputs show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the timer register in the cycle following the one in which the transition was detected. Since it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle (see also section 7.1 "Parallel I/O" for the exact sample time at the port pin P1.7). Note: The prescaler must be off for proper counter operation of timer 2, i.e. T2PS must be 0. In either case, no matter whether timer 2 is configured as timer, event counter, or gated timer, a rolling-over of the count from all 1's to all 0's sets the timer overflow flag TF2 (bit 6 in SFR IRCON, interrupt request control) which can generate an interrupt. lf TF2 is used to generate a timer overflow interrupt, the request flag must be cleared by the interrupt service routine as it could be necessary to check whether it was the TF2 flag or the external reload request flag EXF2 which requested the interrupt (for EXF2 see below). Both request flags cause the program to branch to the same vector address. The input clock to timer 2 is selected by bits T2I0, T2I1, and T2PS as listed in figure 7-35.
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Reload of Timer 2 The reload mode for timer 2 is selected by bits T2R0 and T2R1 in SFR T2CON as listed in figure 7-34 b). Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. The reload will happen in the same machine cycle in which TF2 is set, thus overwriting the count value 0000H. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin T2EX/P1.5. In addition, this transition will set flag EXF2, if bit EXEN2 in SFR IEN1 is set. lf the timer 2 interrupt is enabled, setting EXF2 will generate an interrupt. The external input pin T2EX is sampled in every machine cycle. When the sampling shows a high in one cycle and a low in the next cycle, a transition will be recognized. The reload of timer 2 registers will then take place in the cycle following the one in which the transition was detected.
Figure 7-34 b) Timer 2 in Reload Mode Semiconductor Group 99
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Figure 7-35 Special Function Register T2CON 0CFH 0C8H T2PS 0CEH I3FR 0CDH I2FR 0CCH T2R1 0CBH T2R0 0CAH T2CM 0C9H T2I1 0C8H T2I0 T2CON
These bits are not used in controlling the CCU. Timer 2 control register. Bit-addressable register which controls timer 2 function and compare mode of registers CRC, CC1 to CC3.
Bit T2I1 0 0 1 1 T2R1 0 1 1 T2CM T2PS T2I0 0 1 0 1 T2R0 X 0 1
Symbol Timer 2 input selection No input selected, timer 2 stops Timer function input frequency = fOSC/12 (T2PS = 0) or fOSC/24 (T2PS = 1) Counter function, external input controlled by pin T2/P1.7. Gated timer function, input controlled by pin T2/P1.7 Timer 2 reload mode selection Reload disabled Mode 0: auto-reload upon timer 2 overflow (TF2) Mode 1: reload upon falling edge at pin T2EX/P1.5. Compare mode bit for registers CRC, CC1 through CC3. When set, compare mode 1 is selected. T2CM = 0 selects compare mode 0. Prescaler select bit. When set, timer 2 is clocked in the "timer" or "gated timer" function with 1/24 of the oscillator frequency. T2PS = 0 gates fOSC/12 to timer 2. T2PS must be 0 for the counter operation of timer 2.
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7.5.2
The Compare Timer
This timer - the fourth timer in the SAB 80C517 - is implemented to function as a fast 16-bit time base for the compare registers CM0 to CM7. The compare timer combine with the CMx registers can be employed as high-speed output unit or as a fast 16-bit pulse-width modulator unit. For this case, every CMx register assigned to the compare timer automatically operates in compare mode 0: a compare timer overflow sets the corresponding output line at port 4 to low level, a compare match pulls the pin high again (see also section 7.5.4.1). The minimum resolution attainable at the port 4 outputs is tCYCLE/6 (appr. 166.6 ns at fOSC = 12 MHz). The compare timer is provided with a 16-bit auto-reload and an 8-bit prescaler for a very high flexibility concerning timer period length and input clock frequency. A block diagram of the compare timer is shown in figure 7-36. Input Clock Selection The compare timer receives its input clock from a programmable prescaler which provides eight different input frequencies: fOSC/2, fOSC/4, fOSC/8, fOSC/16, fOSC/32, fOSC/64, fOSC/128, fOSC/256. The selection can be done in a three-bit field (binary coded) in special function register CTCON (see figure 7-37). Register CTCON can be written to at any time, its default value after reset is 00H (that is fOSC/2 input frequency).
Figure 7-36 Compare Timer Block Diagram Semiconductor Group 101
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Programming the Compare Timer in Auto-Reload Operation The compare timer is, once started, a free-running 16-bit timer, which upon overflow is automatically reloaded by the contents of the special function register CTRELL (compare timer reload register, low byte) and CTRELH (compare timer reload register, high byte). An initial writing to the reload register CTRELL (the low byte) starts the timer. If the compare timer is already running, a write-to-CTRELL again triggers an instant reload of the timer, in other words restarts the timer in the cycle following the write instruction with the count being loaded to the reload registers CTRELH/ CTRELL.
Figure 7-37 Compare Timer Control Register CTCON 0E1H T2PS1 - - - CTF CLK2 CLK1 CLK0 CTCON
Compare timer control register. Contains clock selection bits for the compare timer, the compare timer overflow flag and the control bit for the timer 2 prescaler.
Bit CLK2 CLK1 CLK0 CTF T2PS1
Function Compare timer input clock selection. See table below. Compare timer overflow flag. Bit is cleared by hardware. If the compare timer interrupt is enabled, CTF = 1 will cause an interrupt. Prescaler select bit for timer 2 T2PS1 must be 0 for the counter operation of timer 2. CLK1 0 0 1 1 0 0 1 1 CLK0 0 1 0 1 0 1 0 1 Function Compare timer input clock is fOSC/2 Compare timer input clock is fOSC/4 Compare timer input clock is fOSC/8 Compare timer input clock is fOSC/16 Compare timer input clock is fOSC/32 Compare timer input clock is fOSC/64 Compare timer input clock is fOSC/128 Compare timer input clock is fOSC/256
CLK2 0 0 0 0 1 1 1 1
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When the reload register is to be loaded with a 16-bit value, the high byte of CTREL must be written first to ensure a determined start or restart position. Writing to the low byte then triggers the actual reload procedure mentioned above. The 16-bit reload value can be overwritten at any time. Overflow Interrupt of the Compare Timer The compare timer has - as any other timer in the SAB 80C517 - its own interrupt request flag, which is in this case called CTF. This flag is located in register CTCON.CTF and is set when the timer count rolls over from all ones to the reload value. The overflow interrupt eases e.g. software control of pulse width modulated output signals. A periodic interrupt service routine caused by an overflow of the compare timer can be used to load new values in the assigned compare registers and thus change the corresponding PWM output accordingly. Please refer to section 8 for details about the overflow interrupt (enabling, vector address, priority, etc.). 7.5.3 Compare Function in the CCU
The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register. lf the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin. The contents of a compare register can be regarded as 'time stamp' at which a dedicated output reacts in a predefined way (either with a positive or negative transition). Variation of this 'time stamp' somehow changes the wave of a rectangular output signal at a port pin. This may - as a variation of the duty cycle of a periodic signal - be used for pulse width modulation as well as for a continually controlled generation of any kind of square wave forms. In the case of the SAB 80C517, two compare modes are implemented to cover a wide range of possible applications (see section 7.5.4 below). In the SAB 80C517 - thanks to the high number of 13 compare registers and two associated timers - several timer/compare register combinations are selectable. In some of these configurations one of the two compare modes may be freely selected, others, however, automatically establish a compare mode. In the following the two possible modes are generally discussed. This description will be referred to in later sections where the compare registers are described. 7.5.4 Compare Modes of the CCU
As already mentioned, there are only a few compare registers with their corresponding port circuitry which are able to serve both compare modes. In most cases the mode is automatically set depending on the timer which is used as time base or depending on the port which outputs the compare signal.
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7.5.4.1 Compare Mode 0 In mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the port will have no effect. Figure 7-38 shows a functional diagram of a port latch in compare mode 0. The port latch is directly controlled by the two signals timer overflow and compare. The input line from the internal bus and the write-to-latch line are disconnected when compare mode 0 is enabled. Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the inductance of a DC or AC motor). Mode 0 may also be used for providing output clocks with initially defined period and duty cycle. This is the mode which needs the least CPU time. Once set up, the output goes on oscillating without any CPU intervention. Figure 7-39 illustrates the function of compare mode 0. For some information on how to operate a timer/compare register configuration to generate PWM signals (e.g. by using a compare interrupt), please refer to chapter 7.5.5 where more details about the configurations can be found, or to chapter 10 where two application examples are provided.
Figure 7-38 Port Latch in Compare Mode 0 Semiconductor Group 104
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Modulation Range of a PWM Signal and Differences between the Two Timer/Compare Register Configurations in the CCU There are two timer/compare register configurations in the CCU which can operate in compare mode 0 (either timer 2 with a CCx (CRC and CC1 to CC4) register or the compare timer with a CMx register). They basically operate in the same way, but show some differences concerning their modulation range when used for PWM. Generally it can be said that for every PWM generation with n-bit wide compare registers there are 2n different settings for the duty cycle. Starting with a constant low level (0% duty cycle) as the first setting, the maximum possible duty cycle then would be (1 - 1/2n) x 100 % This means that a variation of the duty cycle from 0% to real 100% can never be reached if the compare register and timer register have the same length. There is always a spike which is as long as the timer clock period. In the SAB 80C517 there are two different modulation ranges for the above mentioned two timer/ compare register combinations. The difference is the location of the above spike within the timer period: at the end of a timer period or at the beginning plus the end of a timer period. Please refer to the description of the relevant timer/register combination in section 7.5.5.1 or 7.5.5.2 for details.
Figure 7-39 Function of Compare Mode 0 Semiconductor Group 105
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7.5.4.2 Compare Mode 1 In compare mode 1, the software adaptively determines the transition of the output signal. This mode can only be selected for compare registers assigned to timer 2. lt is commonly used when output signals are not related to a constant signal period (as in a standard PWM generation) but must be controlled very precisely with high resolution and without jitter. In compare mode 1, both transitions of a signal can be controlled. Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity. lf mode 1 is enabled, and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, one can choose whether the output signal is to make a new transition (1-to-0 or 0-to-1, depending on the actual pinlevel) or should keep its old value at the time the timer 2 count matches the stored compare value. Figure 7-40 shows a functional diagram of a timer/compare register/port latch configuration in compare mode 1. In this function, the port latch consists of two separate latches. The upper latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the output latch (and thus to the port pin) in response to a compare match. Note that the double latch structure is transparent as long as the internal compare signal is active. While the compare signal is active, a write operation to the port will then change both latches. This may become important when driving timer 2 with a slow external clock. In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch. For details see also section 7.5.5.1 "Using Interrupts in Combination with the Compare Function". A read-modify-write instruction (see section 7.1) will read the user-controlled "shadow latch" and write the modified value back to this "shadow-latch". A standard read instruction will - as usual - read the pin of the corresponding compare output.
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Figure 7-40 Compare Function of Compare Mode 1 7.5.5 Timer/Compare Register Configurations in the CCU
The compare function and the reaction of the corresponding outputs depend on the timer/compare register combination. Basically, all compare functions implemented in the SAB 80(C)515 can also be used in the SAB 80C517. Furthermore, the SAB 80C517 has nine further compare registers and an additional 16-bit timer, thus providing a high flexibility in assigning compare registers to timers and output lines. Table 7-10 shows possible configurations of the CCU and the corresponding compare modes which can be selected. The following sections describe the function of these configurations.
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Table 7-10 CCU Configurations Assigned Timer Timer 2 Compare Register CRCH/CRCL CCH1/CCL1 CCH2/CCL2 CCH3/CCL3 CCH4/CCL4 CCH4/CCL4 : CCH4/CCL4 CMH0/CML0 : CMH7/CML7 Compare timer CMH0/CML0 : : CMH7/CML7 Compare Output at P1.0/INT3/CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2/CC4 P5.0/CCM0 : P5.7/CCM7 P4.0/CM0 : P4.7/CM7 P4.0/CM0 : : P4.7/CM7 Possible Modes Comp. mode 0, 1 + Reload Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 1 : Comp. mode 1 Comp. mode 1 : Comp. mode 1 Comp. mode 0 (with shadow latches) : : Comp. mode 0 (with shadow latches)
7.5.5.1 Compare Function of Timer 2 with Registers CRC, CC1 to CC4 Compare Function of Registers CRC, CC1 to CC3 The compare function of registers CRC, CC1 to CC3 is completely compatible with the corresponding function of the SAB 80(C)515. Registers CRC, CC1 to CC3 are permanently connected to timer 2. All four registers are multifunctional as they additionally provide a capture (see section 7.5.6) or a reload capability (the CRC register only, see section 7.5.1). A general selection of the function is done in register CCEN (see figure 7-41). For compare function they can be used in compare mode 0 or 1, respectively. The compare mode is selected by setting or clearing bit T2CM in special function register T2CON.
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Figure 7-41 Special Function Register CCEN 0C1H COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAH0 COCAL0 CCEN Compare/capture enable register selects compare or capture function for register CRC, CC1 to CC3.
Bit COCAH0 0 0 1 1 COCAH1 0 0 1 1 COCAH2 0 0 1 1 COCAH3 0 0 1 1 COCAL0 0 1 0 1 COCAL1 0 1 0 1 COCAL2 0 1 0 1 COCAL3 0 1 0 1
Function Compare/capture mode for CRC register Compare/capture disabled Capture on falling/rising edge at pin P1.0/INT3/CC0 Compare enabled Capture on write operation into register CRCL Compare/capture mode for CC register 1 Compare/capture disabled Capture on rising edge at pin P1.1/INT4/CC1 Compare enabled Capture on write operation into register CCL1 Compare/capture mode for CC register 2 Compare/capture disabled Capture on rising edge at pin P1.2/INT5/CC2 Compare enabled Capture on write operation into register CCL2 Compare/capture mode for CC register 3 Compare/capture disabled Capture on rising edge at pin P1.3/INT6/CC3 Compare enabled Capture on write operation into register CCL3
Figure 7-42 and 7-43 show the general timer/compare register/port latch configuration for registers CRC and CC1 to CC4 in compare mode 0 and compare mode 1. Please note that the compare interrupts of registers CRC and CC4 can be programmed to be negative or positive transition activated. Compare interrupts for the CC1 to CC3 registers are always positive transition activated.
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Figure 7-42 Timer 2 with Registers CCx (= CRC and CC1 to CC4) in Compare Mode 0
Figure 7-43 Timer 2 with Registers CCx (= CRC and CC1 to CC4) in Compare Mode 1
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Modulation Range in Compare Mode 0 As already mentioned in the general description of compare mode 0 (section 7.5.4), a 100% variation of the duty cycle of a PWM signal cannot be reached. A time portion of 1/(2n) of an n-bit timer period is always left over. This "spike" may either appear when the compare register is set to the reload value (limiting the lower end of the modulation range) or it may occur at the end of a timer period. In a timer 2/CCx register configuration in compare mode 0 this spike is divided into two halves: one at the beginning when the contents of the compare register is equal to the reload value of the timer; the other half when the compare register is equal to the maximum value of the timer register (here: 0FFFFH). Please refer to figure 7-44 where the maximum and minimum duty cycle of a compare output signal is illustrated. Timer 2 is incremented with the machine clock (fOSC/12), thus at 12-MHz operational frequency, these spikes are both approx. 500 ns long.
Figure 7-44 Modulation Range of a PMW Signal Generated with a Timer 2/CCx Register Combination in Compare Mode 0 The following example shows how to calculate the modulation range for a PWM signal. To calculate with reasonable numbers, a reduction of the resolution to 8-bit is used. Otherwise (for the maximum resolution of 16-bit) the modulation range would be so severely limited that it would be negligible.
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Example: Timer 2 in auto-reload mode; contents of reload register CRC = 0FF00H Restriction of module. Range = 1 x 100% = 0.195% 256 x 2
This leads to a variation of the duty cycle from 0.195% to 99.805% for a timer 2/CCx register configuration when 8 of 16 bits are used. Compare Function of Register CC4; "Concurrent Compare" Compare register CC4 is new in the SAB 80C517 and permanently assigned to timer 2. lt has its own compare/capture enable register CC4EN (see figure 7-47). Register CC4 can be set to operate as any of the other CC registers (see also figures 7-42 and 7-43). Its output pin is P1.4/ CC4/INT2 and it has a dedicated compare mode select bit COMO located in register CC4EN. In addition to the standard operation in compare mode 0 or 1, there is another feature called 'concurrent compare' which is just an application of compare mode 1 to more than one output pin. Concurrent compare means that the comparison of CC4 and timer 2 can manipulate up to nine port pins concurrently. A standard compare register in compare mode 1 normally transfers a preprogrammed signal level to a single output line. Register CC4, however, is able to put a 9-bit pattern to nine output lines. The nine output lines consist of one line at port P1.4 (which is the standard output for register CC4) and an additional eight lines at port 5 (see figure 7-45). Concurrent compare is an ideal and effective option where more than one synchronous output signal is to be generated. Applications including this requirement could among others be a complex multiple-phase stepper motor control as well as the control of ignition coils of a car engine. All these applications have in common that predefined bit-patterns must be put to an output port at a precisely predefined moment. This moment refers to a special count of timer 2, which was loaded to compare register CC4. Figure 7-46 gives an example of how to generate eight different rectangular wave forms at port 5 using a pattern table and a time schedule for these patterns. The patterns are moved into port 5 before the corresponding timer count is reached. The (future) timer count at which the pattern shall appear at the port must be loaded to register CC4. Thus the user can mask each port bit differently depending on whether he wants the output to be changed or not. Concurrent compare is enabled by setting bit COCOEN in special function register CC4EN. A '1' in this bit automatically sets compare mode 1 for register CC4, too. A 3-bit field in special function register CC4EN determines the additional number of output pins at port 5. Port P1.4/CC4/INT2 is used as a standard output pin in any compare mode for register CC4.
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Figure 7-45 "Concurrent Compare" Function of Register CC4
Figure 7-46 Example for a "Concurrent Compare" at Port 5 Semiconductor Group 113
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Figure 7-47 Compare/Capture Enable Register CC4EN 0C9H - COCON2 COCON1 COCON0COCOEN COCAH4 COCAL4 COMO CC4EN
Selects compare or capture function, number of concurrent compares and compare mode of register CC4.
Bit COCAH4 0 0 1 1 COMO COCAL4 0 1 0 1
Function Compare/capture mode for CC4 register Compare/capture disabled Capture on falling/rising edge at pin P1.0/INT2/CC4 Compare enabled Capture on write operation into register CC4L. Compare mode bit. When set compare mode 1 is selected for CC4. COMO = 0 selects compare mode 0. Enables the compare mode 1 and the concurrent compare output for CC4. Setting of this bit automatically sets bit COMO. Selects additional concurrent compare outputs at port 5. See table below.
COCOEN
COCON2 COCON1 COCON0 COCON2 0 0 0 0 1 1 1 1 COCON1 0 0 1 1 0 0 1 1 COCON0 0 1 0 1 0 1 0 1
Function One additional output of CC4 at P5.0 Additional outputs of CC4 at P5.0 to P5.1 Additional outputs of CC4 at P5.0 to P5.2 Additional outputs of CC4 at P5.0 to P5.3 Additional outputs of CC4 at P5.0 to P5.4 Additional outputs of CC4 at P5.0 to P5.5 Additional outputs of CC4 at P5.0 to P5.6 Additional outputs of CC4 at P5.0 to P5.7
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Using Interrupts in Combination with the Compare Function The compare service of registers CRC, CC1, CC2, CC3 and CC4 is assigned to alternate output functions at port pins P1.0 to P1.4. Another option of these pins is that they can be used as external interrupt inputs. However, when using the port lines as compare outputs then the input line from the port pin to the interrupt system is disconnected (but the pin's level can still be read under software control). Thus, a change of the pin's level will not cause a setting of the corresponding interrupt flag. In this case, the interrupt input is directly connected to the (internal) compare signal thus providing a compare interrupt. The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next "compare match". The principle is, that the internal compare signal (generated at a match between timer count and register contents) not only manipulates the compare output but also sets the corresponding interrupt request flag. Thus, the current task of the CPU is interrupted - of course provided the priority of the compare interrupt is higher than the present task priority - and the corresponding interrupt service routine is called. This service routine then sets up all the necessary parameters for the next compare event. Some advantages in using compare interrupts: Firstly, there is no danger of unintentional overwriting a compare register before a match has been reached. This could happen when the CPU writes to the compare register without knowing about the actual timer 2 count. Secondly, and this is the most interesting advantage of the compare feature, the output pin is exclusively controlled by hardware therefore completely independent from any service delay which in real time applications could be disastrous. The compare interrupt in turn is not sensitive to such delays since it loads the parameters for the next event. This in turn is supposed to happen after a sufficient space of time. Please note two special cases where a program using compare interrupts could show a "surprising" behavior: The first configuration has already been mentioned in the description of compare mode 1. The fact that the compare interrupts are transition activated becomes important when driving timer 2 with a slow external clock. In this case it should be carefully considered that the compare signal is active as long as the timer 2 count is equal to the contents of the corresponding compare register, and that the compare signal has a rising and a falling edge. Furthermore, the "shadow latches" used in compare mode 1 are transparent while the compare signal is active. Thus, with a slow input clock for timer 2, the comparator signal is active for a long time (= high number of machine cycles) and therefore a fast interrupt controlled reload of the compare register could not only change the "shadow latch" - as probably intended - but also the output buffer.
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When using the CRC or CC4 register, you can select whether an interrupt should be generated when the compare signal goes active or inactive, depending on the status of bits I3FR or I2FR in T2CON, respectively. Initializing the interrupt to be negative transition triggered is advisive in the above case. Then the compare signal is already inactive and any write access to the port latch just changes the contents of the "shadow-latch". Please note that for CC registers 1 to 3 an interrupt is always requested when the compare signal goes active. The second configuration which should be noted is when compare functions are combined with negative transition activated interrupts. lf the port latch of port P1.0 or P.1.4 contains a 1, the interrupt request flags IEX3 or IEX2 will immediately be set after enabling the compare mode for the CRC or CC4 register. The reason is that first the external interrupt input is controlled by the pin's level. When the compare option is enabled the interrupt logic input is switched to the internal compare signal, which carries a low level when no true comparison is detected. So the interrupt logic sees a 1-to-0 edge and sets the interrupt request flag. An unintentional generation of an interrupt during compare initialization can be prevented if the request flag is cleared by software after the compare is activated and before the external interrupt is enabled. 7.5.5.2 Compare Function of Registers CM0 to CM7 The CCU of the SAB 80C517 contains another set of eight compare registers, an additional timer (the compare timer) and some control SFR in the CCU which have not been described yet. These compare registers and the compare timer are mainly dedicated to PWM applications. The additional compare registers CM0 to CM7, however, are not permanently assigned to the compare timer, each register may individually be configured to work either with timer 2 or the compare timer as shown in table 7-10 on page 133. The flexible assignment of the CMx registers allows an independent use of two time bases where by different application requirements can be met. Any CMx register connected to the compare timer automatically works in compare mode 0 e.g. to provide fast PWM with low CPU intervention. Together with timer 2, CMx registers operate in compare mode 1; the latter configuration, which is described in the next section, allows the CPU to control the compare output transitions directly. The assignment of the eight registers CM0 to CM7 to either timer 2 or to the compare timer is done by an 8-channel 2:1 multiplexer (shown in the general block diagram in figure 7-33). The multiplexer can be programmed by the corresponding bits in special function register CMSEL (see figure 7-48). The compare function itself can individually be enabled in the SFR CMEN (see figure 7-49). Note however that these register are not bit-addressable, which means that the value of single bits can only be changed by AND-ing or OR-ing the register with a certain mask.
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Figure 7-48 Special Function Register CMSEL
0F7H CMSEL.7 CMSEL.6 CMSEL.5 CMSEL.4 CMSEL.3 CMSEL.2 CMSEL.1 CMSEL.0 CMSEL Contains select bits for registers CM0 to CM7. When set, CMLx/CMHx are assigned to the compare timer and compare mode 0 is enabled. The compare registers are assigned to timer 2 if CMSELx = 0. In this case compare mode 1 is selected.
Bit CMSEL.7 CMSEL.6 CMSEL.5 CMSEL.4 CMSEL.3 CMSEL.2 CMSEL.1 CMSEL.0
Function Select bit for CM7 Select bit for CM6 Select bit for CM5 Select bit for CM4 Select bit for CM3 Select bit for CM2 Select bit for CM1 Select bit for CM0
Figure 7-49 Special Function Register CMEN
0F6H
CMEN.7 CMEN.6 CMEN.5 CMEN.4 CMEN.3 CMEN.2 CMEN.1 CMEN.0 CMEN
Contains enable bits for compare registers CM0 to CM7. When set, compare function is enabled and led to the output lines.
Bit CMEN.7 CMEN.6 CMEN.5 CMEN.4 CMEN.3 CMEN.2 CMEN.1 CMEN.0
Function Compare enable bit for CM7 Compare enable bit for CM6 Compare enable bit for CM5 Compare enable bit for CM4 Compare enable bit for CM3 Compare enable bit for CM2 Compare enable bit for CM1 Compare enable bit for CM0
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Flrst Configuration: CMx Registers Assigned to the Compare Timer Every CMx register switched to the compare timer as a time base operates in compare mode 0 and uses a port 4 pin as an alternate output function (see table 7-8: Alternate Port Functions of the CCU). - Modulation Range in Compare Mode 0 In the general description of compare mode 0 (section 7.5.4) and in the description of the timer 2/ CCx register configuration (section 7.5.5.1) it was mentioned that a compare output is restricted in its maximum or minimum duty cycle. There is always a time portion of 1/2n (at n-bit timer length) which is left over. This "spike" may either appear when the compare register is set to the reload value (limiting the lower end of the modulation range) or it may occur at the end of a timer period as realized in this configuration. In a compare timer/CMx register configuration, the compare output is set to a constant high level if the contents of the compare registers are equal to the reload register (CTREL). The compare output shows a high level for one timer clock period when a CMx register is set to 0FFFFH. Thus, the duty cycle can be varied from 0.xx% to 100% depending on the resolution selected (see calculation example in section 7.5.5.1). Please refer to figure 7-50 where the maximum and minimum duty cycle of a compare output signal is illustrated. One clock period of the compare timer is equal to one machine state (= 2 oscillator periods) if the prescaler is off. Thus, at 12-MHz operational frequency the spike is approx. 166.6 ns long. - The "Timer Overflow Controlled" Loading There is one great difference between a CMx register and the other previously described compare registers: compare outputs controlled by CMx registers have no dedicated interrupt function. They use a "timer overflow controlled loading" (further on called "TOC loading") to reach the same performance as an interrupt controlled compare. To show what this "TOC loading" is for, it will be explained more detailed in the following: The main advantage of the compare function in general is that the controller's outputs are precisely timed by hardware, no matter which task is running on the CPU. This in turn means that the CPU normally does not know about the timer count. So, if the CPU writes to a compare register only in relation to the program flow, then it could easily be that a compare register is overwritten before the timer had the chance to reach the previously loaded compare value. Hence, there must be something to "synchronize" the loading of the compare registers to the running timer circuitry. This could either be an interrupt caused by the timer circuitry (as described before) or a special hardware circuitry.
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Figure 7-50 Modulation Range of a PWM Signal Generated with a Compare Timer/CMx Register Combination Thus "TOC-Ioading" means that there is dedicated hardware in the CCU which synchronizes the loading of the compare registers CMx in such a way that there is no loss of compare events. lt also relieves the CPU of interrupt load. What does this hardware look like: A CMx compare register in compare mode 0 consists of two latches. When the CPU tries to access a CMx register it only addresses a register latch and not the actual compare latch which is connected to the comparator circuit. The contents of the register latch may be changed by the CPU at any time because this change would never affect the compare event for the current timer period. The compare latch (the "actual" latch) holds the compare value for the present timer period. Thus the CPU only changes the compare event for the next timer period since the loading of the latch is performed by the timer overflow signal of the compare timer. This means for an application which uses several PWM outputs that the CPU does not have to serve every single compare line by an individual interrupt. lt only has to watch the timer overflow of the compare timer and may then set up the compare events of all compares for the next timer period. This job may take the whole current timer period since the TOC loading prevents unintentional overwriting of the actual (and prepared) value in the compare latch.
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Figure 7-51 Compare Function of a CMx Register Assigned to the Compare Timer Figure 7-51 shows a more detailed block diagram of a CMx register connected to the compare timer. lt illustrates that the CPU can only access the special function register CMx; the actual compare latch is, however, loaded at timer overflow. The timer overflow signal also sets an interrupt request flag (CTF in register CTCON) which may be used to inform the CPU by an interrupt that a new timer cycle has started and that the compare values for the next cycle may be programmed from now on. The activation of the TOC loading depends on a few conditions described in the following. A TOC loading is performed only if the CMLx register has been changed by the CPU. A write instruction to the low byte of the CMx register is used to enable the loading. The 8-bit architecture of the SAB 80C517 requires such a defined enable mechanism because 16bit values are to be transferred in two portions (= two instructions). Imagine the following situation: one instruction (e.g. loading the low byte of the compare register) is executed just before timer overflow and the other instruction (loading the high byte) after the overflow. lf there were no "rule", the TOC loading would just load the new low byte into the compare latch. The high byte - written after timer overflow - would have to wait till the next timer overflow.
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The mentioned condition for TOC loading prevents such undesired behavior. lf the user writes the high byte first then no TOC loading will happen before the low byte has been written - even if there is a timer overflow in between. lf the user just intends to change the low byte of the compare latch then the high byte may be left unaffected. Summary of the above description of the TOC loading: - The CMx registers are - when switched to the compare timer - protected from direct loading by the CPU. A register latch couple provides a defined load time at timer overflow. - Thus, the CPU has a full timer period to load a new compare value: there is no danger of overwriting compare values which are still needed in the current timer period. - When writing a 16-bit compare value, the high byte should be written first since the write-tolow-byte instruction enables a 16-bit wide TOC loading at next timer overflow. - lf there was no write access to a CMx low byte then no TOC loading will take place. - Because of the TOC loading, all compare values written to CMx registers are only activated in the next timer period. Initializing the Compare Register/Compare Latch Circuit Normally when the compare function is desired the initialization program would just write to the compare register (called 'register latch'). The compare latch itself cannot be accessed directly by a move instruction, it is exclusively loaded by the timer overflow signal. In some very special cases, however, an initial loading of the compare latch could be desirable. lf the following sequence is observed during initialization then latches, the register and the compare latch, can be loaded before the compare mode is enabled.
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Action: Select compare mode 1 (CMSEL.x = 0). Move the compare value for the first timer period to the compare register CMx (high byte first). Switch on compare mode 0 (CMSEL.x = 1). Move the compere value for the second timer period to the compare register. Enable the compare function (CMEN.x = 1) Set up the prescaler for the compare timer. Set specific compare output to low level (CLR P4.x) Start the compare timer with a desired value (write-to-CTREL) Second Configuration CMx Registers Assigned to Timer 2
Comment: This is also the default value after reset. In compare mode 1 latch is loaded directly after a write-to-CMLx. Thus the value slips directly into the compare latch. Now select the rigth compare mode. The register latch is loaded. This value is used after the first timer overflow.
The compare output is switched to low level.
Compare function is initialized. The output will oscillate.
Any CMx register switched to timer 2 as a time base operates in compare mode 1. In this case CMx registers behave like any other compare register connected to timer 2 (e.g. the CRC or CCx registers). Please refer to the above description of compare mode 1 for further details. Since there are no dedicated interrupts for the CMx compare outputs, again a buffered compare register structure is used to determine an exact 16-bit wide loading of the compare value: the compare value is transferred to the actual compare latches at a write-to-CMLx instruction (low byte of CMx). Thus, the CMx register is to be written in a fixed order, too: high byte first, low byte second. lf the high byte may remain unchanged it is sufficient to load only the low byte. See figure 7-52, block diagram of a CMx register connected to timer 2.
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Figure 7-52 CMx-Register Assigned to Timer 2 7.5.6 Capture Function in the CCU
Each of the four compare/capture registers CC1 to CC4 and the CRC register can be used to latch the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this function. In mode 0, an external event latches the timer 2 contents to a dedicated capture register. In mode 1, a capture will occur upon writing to the low order byte of the dedicated 16-bit capture register. This mode is provided to allow the software to read the timer 2 contents "on-thefly". In mode 0, the external event causing a capture is - for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1 - for the CRC and CC4 register: a positive or negative transition at the corresponding pins, depending on the status of the bits I3FR and I2FR in SFR T2CON. lf the edge flags are cleared, a capture occurs in response to a negative transition; if the edge flags are set a capture occurs in response to a positive transition at pins P1.0/ INT3/ CC0 and P1.4/ INT2/ CC4.
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In both cases the appropriate port 1 pin is used as input and the port latch must be programmed to contain a one (1). The external input is sampled in every machine cycle. When the sampled input shows a low (high) level in one cycle and a high (low) in the next cycle, a transition is recognized. The timer 2 contents is latched to the appropriate capture register in the cycle following the one in which the transition was identified. In mode 0 a transition at the external capture inputs of registers CC0 to CC4 will also set the corresponding external interrupt request flags IEX2 to IEX6. lf the interrupts are enabled, an external capture signal will cause the CPU to vector to the appropriate interrupt service routine. In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The value written to the dedicated capture register is irrelevant for this function. The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction. In this mode no interrupt request will be generated. Figures 7-53 and 7-54 show functional diagrams of the capture function of timer 2. Figure 7-53 illustrates the operation of the CRC or CC4 register, while figure 7-54 shows the operation of the compare/capture registers 1 to 3. The two capture modes can be established individually for each capture register by bits in SFR CCEN (compare/capture enable register) and CC4EN (compare/capture 4 enable register). That means, in contrast to the compare modes, it is possible to simultaneously select mode 0 for one capture register and mode 1 for another register . The bit positions and functions of CCEN are listed in figure 7-41, the one for CC4EN in figure 7-47.
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Figure 7-53 Capture with Registers CRC, CC4
Figure 7-54 Capture with Registers CC1 to CC3
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7.6
Arithmetic Unit
This on-chip arithmetic unit of the SAB 80C517 provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are unsigned integer operations. The arithmetic unit (further on also called MDU for "Multiplication/Division Unit") has been integrated to support the 8051 core of the SAB 80C517 in real-time control applications. lt can increase the execution speed of math-intensive software routines by factor 5 to 10. The MDU is handled by seven registers, which are memory mapped as special function registers like any other registers for peripheral control. Therefore, the arithmetic unit allows operations concurrently to and independent of the CPU's activity. The following table describes the four general operations the MDU is able to perform:
Operation 32bit/16bit 16bit/16bit 16bit x 16bit 32-bit normalize 32-bit shift L/R
Result 32bit 16bit 32bit - -
Remainder 16bit 16bit - - -
Execution Time 6 tCY 1) 4 tCY 1) 4 tCY 1) 6 tCY 2) 6 tCY 2)
1) 1 tCY = 1 microsecond at 12-MHz oscillator frequency 2) The maximal shift speed is 6 shifts per machine cycle
7.6.1
Programming the MDU
Operating Registers of the MDU The seven SFR of the MDU consist of registers MD0 to MD5, which contain the operands and the result (or the remainder, resp.) and one control register called ARCON. Thus MD0 to MD5 are used twofold: - for the operands before a calculation has been started and - for storage of the result or remainder after a calculation. This means that any calculation of the MDU overwrites its operands. lf a program needs the original operands for further use, they should be stored in general purpose registers in the internal RAM.
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Operation of the MDU The MDU can be regarded as a special coprocessor for multiplication, division and shift. Its operations can be divided into three phases (see also figure 7-55): 1) Loading the MDx registers 2) Executing the calculation 3) Reading the result from the MDx registers During phase two, the MDU works on its own parallelly to the CPU. Execution times of the above table refer to this phase. Because of the fast operation and the determined execution time for SAB 80C517's instructions, there is no need for a busy flag. The CPU may execute a determined number of instructions before the result is fetched. The result and the remainder of an operation may also be stored in the MDx registers for later use. Phase one and phase three require CPU activity. In these phases the CPU has to transfer the operands and fetch the results.
Figure 7-55 Operating Phases of the MDU
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How to Select an Operation The MDU has no dedicated instruction register (only for shift and normalize operations, register ARCON is used in such a way). The type of calculation the MDU has to perform is selected following the order in which the MDx registers are written to (see table 7-11). This mechanism also reduces execution time spent for controlling the MDU. Hence, a special write sequence selects an operation. The MDU monitors the whole write and read-out sequence to ensure that the CPU has fetched the result correctly and was not interrupted by another calculation task. (See section 7.6.4 "The Error Flag"). Thus, a complete operation lasts from writing the first byte of the operand in phase 1 until reading the last byte of the result in phase 3. 7.6.2 Multiplication/Division
The general mechanism to start an MDU activity has been described above. The following description of the write and read sequences adds to the information given in the table below where the write and read operations necessary for a multiplication or division are listed.
Table 7-11 Programming the MDU for Multiplication and Division Operation First Write 32Bit/16Bit MD0 MD1 MD2 MD3 MD4 MD5 MD0 MD1 MD2 MD3 MD4 MD5 D'endL D'end D'end D'endH D'orL D'orH QuoL Quo Quo QuoH RemL RemH 16Bit/16Bit MD0 MD1 MD4 MD5 MD0 MD1 MD4 MD5 D'endL D'endH D'orL D'orH QuoL QuoH RemL RemH 16Bit x 16Bit MD0 MD4 MD1 MD5 MD0 MD1 MD2 MD3 PrH M'andL M'orL M'andH M'orH PrL
Last Write First Read
Last Read
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Write Sequence The first and the last write operation in phase one are fixed for every calculation of the MDU. All write operations inbetween determine the type of MDU calculation. - A write-to-MD0 is the first transfer to be done in any case. This write resets the MDU and triggers the error flag mechanism (see below). - The next two or three write operations select the calculation type (32bit/16bit, 16bit/16bit, 16bit x 16bit) The last write-to-MD5 finally starts the selected MUL/DIV operation Read Sequence - Any read-out of the MDx registers should begin with MD0 - The last read from MD5 (division) or MD3 (multiplication) determines the end of a whole calculation and releases the error flag mechanism. There is no restriction on the time within which a calculation must be completed. The CPU is allowed to continue the program simultaneously to phase 2 and to fetch the result bytes at any time. lf the user's program takes care that interrupting a calculation is not possible, monitoring of the calculation process is probably not needed. In this case, only the write sequence must be observed. Any new write access to MD0 starts a new calculation, no matter whether the read-out of the former result has been completed or not. 7.6.3 Normalize and Shift
Register ARCON controls an up to 32-bit wide normalize and shift operation in registers MD0 to MD3. lt also contains the overflow flag and the error flag which are described in the next two sections. Figure 7-56 illustrates special function register ARCON. Write Sequence - A write-to-MD0 is also the first transfer to be done for normalize and shift. This write resets the MDU and triggers the error flag mechanism (see below). - To start a shift or normalize operation the last write must access register ARCON.
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Read Sequence - The order in which the first three registers MD0 to MD2 are read is not critical - The last read from MD3 determines the end of a whole shift or normalize procedure and releases the error flag mechanism. Note: Any write access to ARCON triggers a shift or normalize operation and therefore changes the contents of registers MD0 to MD3 !
Figure 7-56 Register ARCON
0EFH
MDEF MDOV
SLR
SC.4
SC.3
SC.2
SC.1
SC.0
ARCON
Arithmetic control register. Contains control flags and the shift counter of the MDU. Triggers a shift or a normalize operation in register MD0 to MD3 when being written to.
Bit MDEF
Function Error flag. Indicates an improperly performed operation. MDEF is set by hardware when an operation is retriggered by a write access to MDx before the first operation has been completed. MDEF is automatically cleared after being read. Overflow flag. Exclusively controlled by hardware. MDOV is set by following events: - division by zero - multiplication with a result greater than 0FFFFH. Shift direction bit. When set, shift right is performed. SLR = 0 selects shift left operation. Shift counter. When preset with 00000B, normalizing is selected. After operation SC.0 to SC.4 contain the number of normalizing shifts performed. When set with a value 0, shift operation is started. The number of shifts performed is determined by the count written to SC.0 to SC.4.
MDOV
SLR SC.4 SC.3 SC.2 SC.1 SC.0
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Normalizing Normalizing is done on an integer variable stored in MD0 (least significant byte) to MD3 (most significant byte). This feature is mainly meant to support applications where floating point arithmetic is used. "To normalize" means, that all reading zeroes of an integer variable in registers MD0 to MD3 are removed by shift left operations. The whole operation is completed when the MSB (most significant bit) contains a '1'. To select a normalize operation, the five bit field ARCON.0 to ARCON.4 must be cleared. That means, a write-to-ARCON instruction with the value XXX0 0000B starts the operation. After normalizing, bits ARCON.0 to ARCON.4 contain the number of shift left operations which were done. This number may further on be used as an exponent. The maximum number of shifts in a normalize operation is 31 ( = 25 - 1). The operation takes six machine cycles at most, that means 6 microseconds at 12 MHz. Shifting In the same way - by a write-to-ARCON instruction - a shift left/right operation can be started. In this case register bit SLR (ARCON.5) has to contain the shift direction, and ARCON.0 to ARCON.4 the shift count (which must not be 0, otherwise a normalize operation would be executed). During shift, zeroes come into the left or right end of the registers MD0 or MD3, respectively. The first machine cycle of a shift left/right operation executes four shifts, while all following cycles perform 6 shifts. Hence, a 31-bit shift takes 6 microseconds at 12 MHz. Completion of both operations, normalize and shift, can also be controlled by the error flag mechanism described in 7.6.4. The error flag is set if one of the relevant registers (MD0 through MD3) is accessed before the previously commenced operation has been completed. For proper operation of the error flag mechanism, it is necessary to take care that the right write or read sequence to or from registers MD0 to MD3 (see table 7-12) is maintained.
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Table 7-12 Programming a Shift or Normalize Operation Operation First write Normalize, Shift Left, Shift Right MD0 MD1 MD2 MD3 ARCON MD0 MD1 MD2 MD3 least significant byte
Last write First read
most significant byte start of conversion least significant byte
Last read 7.6.4
most significant byte
The Overflow Flag
An overflow flag is provided for some exceptions during MDU calculations. There are three cases where flag MDOV ARCON.6 is set by hardware: - Division by zero - Multiplication with a result greater then 0000 FFFF H (= auxiliary carry of the lower 16bit) - Start of normalizing if the most significant bit of MD3 is set (MD3.7 = 1). Any operation of the MDU which does not match the above conditions clears the overflow flag. Note that the overflow flag is exclusively controlled by hardware. lt cannot be written to. 7.6.5 The Error Flag
An error flag, bit MDEF in register ARCON (figure 7-56), is provided to indicate whether one of the arithmetic operations of the MDU (multiplication, division, normalize, shift left/right) has been restarted or interrupted by a new operation. This can possibly happen e.g. when an interrupt service routine interrupts the writing or reading sequence of the arithmetic operation in the main program and starts a new operation. Then the contents of the corresponding registers are indeterminate (they would normally show the result of the last operation executed).
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In this case the error flag can be used to indicate whether the values in the registers MD0 to MD5 are the expected ones or whether the operation must be repeated. For a multiplication/division, the error flag mechanism is automatically enabled with the first write instruction to MD0 (phase 1). According to the above described programming sequences, this is the first action for every type of calculation. The mechanism is disabled with the final read instruction from MD3 or MD5 (phase 3). Every instruction which rewrites MD0 (and therefore tries to start a new calculation) in phases 1 through 3 of the same process sets the error flag. The same applies for any shift operation (normalize, shift left/right). The error flag is set if the user's program reads one of the relevant registers (MD0 to MD3) or if it writes to MD0 again before the shift operation has been completed. Please note that the error flag mechanism is just an option to monitor the MDU operation. lf the user's program is designed such that an MDU operation cannot be interrupted by other calculations, then there is no need to pay attention to the error flag. In this case it is also possible to change the order in which the MDx registers are read, or even to skip some register read instructions. Concerning the shift or normalize instructions, it is possible to read the result before the complete execution time of six machine cycles has passed (e.g. when a small number of shifts has been programmed). All of the above "illegal" actions would set the error flag, but on the other hand do not affect a correct MDU operation. The user has just to make sure that everything goes right. The error flag (MDEF) is located in ARCON and can be read only. lt is automatically cleared after being read.
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7.7
Power Saving Modes
The SAB 80C517 provides - due to Siemens ACMOS technology - three modes in which power consumption can be significantly reduced. - Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. - Power-down mode Operation of the SAB 80C517 is completely stopped, the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. - Slow-down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by eight. This slows down all parts of the controller, the CPU and all peripherals, to 1/8th of their normal operating frequency. Slowing down the frequency greatly reduces power consumption. All of these modes - a detailed description of each is given in the following sections - are entered by software. Special function register PCON (power control register, see figure 7-57) is used to select one of these modes. These power saving modes, especially the power-down mode, replace the hardware power-down supply for the internal RAM via a dedicated pin, as it is common with NMOS microcontrollers. During the power saving modes, the power supply for the SAB 80C517 is again via all VCC pins. There is no further dedicated pin for power-down supply. For the SAB 80C517 several provisions have been made to quality it for both electrically noisy environments and applications requiring high system security. In such applications unintentional entering of the power saving modes must be absolutely avoided. A power saving mode would reduce the controller's performance (in the case of slow-down mode) or even stop any operation (in the case of power-down mode). This situation might be fatal for the system, which is controlled by the microcontroller. Such critical applications often use the watchdog timer to prevent the system from program upsets. Then, an accidental entering of the power saving modes would even stop the watchdog timer and would circumvent the watchdog timer's task of system protection.
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Hardware Enable for the Use of the Power Saving Modes To provide power saving modes together with effective protection against unintentional entering of these modes, the SAB 80C517 has an extra pin disabling the use of the power saving modes. As this pin will most likely be used only in critical applications it is combined with an automatic start of the watchdog timer (see the description in section 7.8 "Fail Save Mechanisms"). This pin is called PE/SWD (powers saving enable/start watchdog timer) and its function is as follows: PE/SWD = 1 (logic high level) - Use of the power saving modes is not possible. The instruction sequences used for entering these modes will not affect the normal operation of the device. - lf and only if PE/SWD is held at high level during reset, the watchdog timer is started immediately after reset is released. PE/SWD = 0 (logic low level) - All power saving modes can be activated as described in the following sections - The watchdog timer has to be started by software if system protection is desired. When left unconnected, the pin PE/SWD is pulled to high level by a weak internal pullup. This is done to provide system protection by default. The logic level applied to pin PE/SWD can be changed during program execution in order to allow or block the use of the power saving modes without any effect on the on-chip watchdog circuitry; (the watchdog timer is started only if PE/SWD is on high level at the moment when reset is released; a change at PE/SWD during program execution has no effect on the watchdog timer; this only enables or disables the use of the power saving modes.). A change of the pin's level is detected in state 3, phase 1. A Schmitt trigger is used at the input to reduce susceptibility to noise. In addition to the hardware enable/disable of the power saving modes, a double-instruction sequence which is described in the corresponding sections is necessary to enter power-down and idle mode. The combination of all these safety precautions provide a maximum of system protection.
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Application Example for Switching Pin PE/SWD For most applications in noisy environments, components external to the chip are used to give warning of a power failure or a turn off of the power supply. These circuits could be used to control the PE/SWD pin. The possible steps to go into power-down mode could then be as follows: - A power-fail signal forces the controller to go into a high priority interrupt routine. This interrupt routine saves the actual program status. At the same time pin PE/SWD is pulled low by the power-fail signal. - Finally the controller enters power-down mode by executing the relevant double-instruction sequence. 7.7.1 Idle Mode
In idle mode the oscillator of the SAB 80C517 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial channels, the A/D converter, the oscillator watchdog, the division/multiplication unit and all timers, except for the watchdog timer, are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The reduction of power consumption, which can be achieved by this feature, depends on the number of peripherals running. lf all timers are stopped and the A/D converter and the division/ multiplication unit are not running, maximum power reduction can be achieved. This state is also the test condition for the idle ICC (see the DC characteristics in the data sheet). Thus, the user has to take into account that the right peripheral continues to run or is stopped, respectively, during idle. Also, the state of all port pins - either the pins controlled by their latches or controlled by their secondary functions - depends on the status of the controller when entering idle. Normally the port pins hold the logical state they had at the time idle was activated. lf some pins are programmed to serve their alternate functions they still continue to output during idle if the assigned function is on. This applies for the compare outputs as well as for the system clock output signal and the serial interface in case the latter could not finish reception or transmission during normal operation. The control signals ALE and PSEN are held at logic high levels (see table 7-13). During idle, as in normal operating mode, the ports can be used as inputs. Thus, a capture or reload operation as well as an A/D conversion can be triggered, the timers can be used to count external events and external interrupts can be detected.
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Table 7-13 Status of External Pins During Idle and Power-Down Mode Outputs Idle ALE PSEN Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 High High Data Data/alternate outputs Data Data/alternate outputs Data/alternate outputs Data/alternate outputs Data/alternate outputs Last Instruction Executed from Internal Code Memory Power-down Low Low Data Data/ last output Data Data/ last output Data last output Data/ last output Data/ last output Idle High High Float Data/alternate outputs Address Data/alternate outputs Data/alternate outputs Data/alternate outputs Data/alternate outputs Last Instruction Executed from External Code Memory Power-down Low Low Float Data/ last output Data Data/ last output Data/ last output Data/ last output Data/ last output
The watchdog timer is the only peripheral which is automatically stopped during idle. The idle mode makes it possible to "freeze" the processor's status for a certain time or until an external event causes the controller to go back into normal operating mode. Since the watchdog timer is stopped during idle mode, this useful feature of the SAB 80C517 is provided even if the watchdog function is used simultaneously. lf the idle mode is to be used the pin PE/SWD must be held low. Entering the idle mode is to be done by two consecutive instructions immediately following each other. The first instruction has to set the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction has to set the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and IDLS will not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after having been set. lf one of these register bits is read the value shown is zero (0). Figure 7-57 shows special function register PCON. This double-instruction sequence is implemented to minimize the chance of unintentionally entering the idle mode. Note that PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle mode is to be done by byte handling instructions.
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The following instruction sequence may serve as an exemple: ORL ORL PCON,#00000001B PCON,#00100000B ;Set bit IDLE, ;bit IDLS must not be set ;Set bit IDLS, ;bit IDLE must not be set
The instruction that sets bit IDLS is the last instruction executed before going into idle mode. Terminating the Idle Mode - The idle mode can be terminated by activation of any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that set the bit IDLS. - The other possibility of terminating the idle mode is a hardware reset. Since the oscillator is still running, the hardware reset is held active for only two machine cycles for a complete reset.
Figure 7-57 Special Function Register PCON (Address 87H) 87H SMOD PDS IDLS SD GF1 GF0 PDE IDLE PCON
These bits are not used in controlling the power saving modes
Bit PDS IDLS SD GF1 GF0 PDE IDLE
Function Power-down start bit. The instruction that sets the PDS flag bit is the last instruction before entering the power-down mode. IDLE start bit. The instruction that sets the IDSL flag bit is the last instruction before entering the idle mode. When set, the slow-down mode is enabled. General purpose flag General purpose flag Power-down enable bit. When set, starting the power-down mode is enabled. Idle mode enable bit. When set, starting the idle mode is enabled.
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7.7.2
Power-Down Mode
In the power-down mode, the on-chip oscillator is stopped. Therefore, all functions are stopped, only the contents of the on-chip RAM and the SFR's are held. The port pins controlled by their port latches output the values that are held by their SFR'S. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power-down mode; when enabled, the clockout signal (P1.6/CLKOUT) will stop at low level. ALE and PSEN are held at logic low level (see table 7-13). lf the power-down mode is to be used, the pin PE/SWD must be held low. Entering the power-down mode is done by two consecutive instructions immediately following each other. The first instruction has to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6). The following instruction has to set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent setting of both bits, PDE and PDS, will not initiate the power-down mode. Bit PDE and PDS will automatically be cleared after having been set and the value shown when reading one of these bits is always zero (0). Figure 7-57 shows the special function register PCON. This doubleinstruction sequence is implemented to minimize the chance of unintentional entering the powerdown mode, which could possibly "freeze" the chip's activity in an undesired status. Note that PCON is not a bit-addressable register, so the above mentioned sequence for entering the power-down mode is composed of byte handling instructions. The following instruction sequence may serve as an example: ORL ORL PCON,#00000010B PCON,#01000000B ;Set bit PDE, ;bit PDS must not be set ;Set bit PDS, ;bit PDE must not be set
The instruction that sets bit PDS is the last instruction executed before going into power-down mode. lf idle mode and power-down mode are invoked simultaneously, the power-down mode takes precedence. The only exit from power-down mode is a hardware reset. Reset will redefine all SFR'S, but will not change the contents of the internal RAM. In the power-down mode, VCC can be reduced to minimize power consumption. Care must be taken, however, to ensure that VCC is not reduced before the power-down mode is invoked, and that VCC is restored to its normal operating level before the power-down mode is terminated. The reset signal that terminates the power-down mode also frees the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset).
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7.7.3
Slow-Down Mode
In some applications, where power consumption and dissipation is critical, the controller might run for a certain time at reduced speed (e.g. if the controller is waiting for an input signal). Since in CMOS devices there is an almost linear interdependence of the operating frequency and the power supply current, a reduction of the operating frequency results in reduced power consumption. In the slow-down mode all signal frequencies that are derived from the oscillator clock are divided by eight. This also includes the clockout signal at pin P1.6/CLKOUT. lf the slow-down mode is to be used the pin PE/SWD must be held low. The slow-down mode is entered by setting bit SD (PCON.4), see figure 7-57. The controller actually enters the slow-down mode after a short synchronization period (max. two machine cycles). The slow-down mode can be used together with idle and power-down mode. The slow-down mode is disabled by clearing bit SD.
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7.8
Fail Save Mechanisms
The SAB 80C517 offers two on-chip peripherals which monitor the program flow and ensure an automatic "fail-safe" reaction for cases where the controller's hardware fails or the software hangs up: - A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds up to approx. 1.1 seconds at 12 MHz. The SAB 80C517's WDT is a superset of the SAB 80515 watchdog. - An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into the reset state if the on-chip oscillator fails.
7.8.1
Programmable Watchdog Timer
To protect the system against software upset, the user's program has to clear this watchdog within a previously programmed time period. lf the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. lt also times out if a software error is based on hardware-related problems. The watchdog timer in the SAB 80C517 is a 15-bit timer, which is incremented by a count rate of either fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). That is, the machine clock is divided by a series arrangement of two prescalers, a divide-by-two and a divide-by-16 prescaler (see figure 7-58). The latter is enabled by setting bit WDTREL.7. Immediately after start (see next section for the start procedure), the watchdog timer is initialized to the reload value programmed to WDTREL.0 - WDTREL.6. After an external HW or HWPD reset, an oscillator power on reset, or a watchdog timer reset, register WDTREL is cleared to 00H. The lower seven bits of WDTREL can be loaded by software at any time. Examples (given for a 12-MHz oscillator frequency):
WDTREL = 00H
Time-Out Period 65.535 ms
Comments This is the default value and coincides with the watchdog period of the SAB 80515 Maximum time period Minimum time period
80H 7FH
1.1 s 512 s
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Starting the Watchdog Timer There are two ways to start the watchdog timer depending on the level applied to pin PE/SWD (pin 4). This pin serves two functions, because it is also used for blocking the power saving modes. For details see chapter 7.7. - The First Possibility of Starting the Watchdog Timer The automatic start of the watchdog timer directly after an external HW reset is a hardware start initialized by strapping pin 4 (PE/SWD) to VCC. In this case the power-saving modes (power-down mode, idle mode and slow-down mode) are also disabled and cannot be started by software. The self-start of the watchdog timer by a pin option has been implemented to provide high system security in electrically very noisy environments. Note: The automatic start of the watchdog timer is only performed if PE/SWD (power-save enable/start watchdog timer) is held at high level while reset is active. A positive transition at this pin during normal program execution will not start the watchdog timer. Furthermore, when using the hardware start, the watchdog timer starts running with its default timeout period. The value in the reload register WDTREL, however, can be overwritten at any time to set any time-out period desired. - The Second Possibility of Starting the Watchdog Timer The watchdog timer can also be started by software. This method is compatible to the start procedure in the SAB 80(C)515. Only setting of bit SWDT in special function register IEN1 (figure 7-61) starts the watchdog timer. Starting the watchdog timer does not automatically reload the WDTREL register into the watchdog timer registers WDTL/WDTH. A reload of WDTREL occurs only when using the double instruction refresh sequence SETB WDT/SETB SWDT. Using the software start, the time-out period can be programmed before the watchdog timer starts running. Note that once the watchdog timer has been started it cannot be stopped by anything but an external hardware reset through pin 10 with a low level applied to pin PE/SWD. Refreshing the Watchdog Timer At the same time the watchdog timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT (IEN0.6) and by the next instruction setting SWDT (IEN1.6). Bit WDT will automatically be cleared during the second machine cycle after having been set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g. SETB SWDT). This double-instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog.
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The reload register WDTREL can be written to at any time, as already mentioned. Therefore, a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer. Thus a wrong reload value caused by a possible distortion during the write operation to the WDTREL can be corrected by software.
Figure 7-58 Block Diagram of the Programmable Watchdog Timer Figure 7-59 Special Function Register WDTREL 086H Watchdog timer reload register WDTREL
Bit WDTREL.7
Function Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler (see figure 7-58). Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT.
WDTREL.6 to WDTREL.0
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On-Chip Peripheral Components
Watchdog Reset and Watchdog Status Flag lf the software fails to clear the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFC H. The duration of the reset signal then depends on the prescaler selection (either 8 cycles or 128 cycles). This internal reset differs from an external one only in so far as the watchdog timer is not disabled and bit WDTS (watchdog timer status, bit 6 in special function register IP0) is set. Figure 7-62 shows a block diagram of all reset requests in the SAB 80C517 and the function of the watchdog status flags. The WDTS flag is a flip-flop, which is set by a watchdog timer reset and cleared by an external HW reset. Bit WDTS allows the software to examine from which source the reset was activated. The watchdog timer status flag can also be cleared by software.
Figure 7-60 Special Function Register IEN0 0AFH 0A8H EAL 0AEH WDT 0ADH ET2 0ACH ES0 0ABH ET1 0AAH EX1 0A9H ET0 0A8H EX0 IEN0
These bits are not used in controlling the fail-safe mechanisms.
Bit WDT
Function Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer.
Figure 7-61 Special Function Register IEN1 0BFH 0BEH 0BDH EX6 0BCH EX5 0BBH EX4 0BAH EX3 0B9H EX2 0B8H EADC IEN1
0B8H EXEN2 SWDT
These bits are not used in controlling the fail-safe mechanisms.
Bit SWDT
Function Watchdog timer start flag. Set to activate the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed.
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On-Chip Peripheral Components
Figure 7-62 Watchdog Status Flags and Reset Requests Figure 7-63 Special Function Register IP0 0A9H OWDS WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 IP0
These bits are not used in controlling the fail-safe mechanisms.
Bit OWDS
Function Oscillator watchdog timer status flag. Set by hardware when an oscillator watchdog reset occured. Can be cleared or set by software Watchdog timer status flag. Set by hardware when a watchdog timer reset occured. Can be cleared or set by software
WDTS
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On-Chip Peripheral Components
7.8.2
Oscillator Watchdog
What happens in a microcontroller system it the controller's on-chip oscillator stops working? This failure e.g. caused by a broken crystal, an open connection to the crystal, or a long-term disturbance normally leaves the system in a random, undetermined state. The SAB 80C517 provides a "failsafe" reaction upon an oscillator failure. lf the on-chip oscillator frequency falls below a certain limit due to a hardware defect, the oscillator watchdog initiates an internal reset. This reset state is maintained until the on-chip oscillator is working again. This ensures a maximum of system protection with a minimum of susceptibility to distortion or to operating errors. In the reset state all port pins of the SAB 80C517 show a '1'. The oscillator watchdog consists of an integrated RC oscillator combined with a frequency comparator. lf the on-chip oscillator's frequency falls below the frequency of the RC oscillator, the comparator generates a signal which initiates a reset. The RC oscillator runs with a frequency of typically 300 kHz and works without any external components. lt also determines, as long as it is used, the lower limit of the SAB 80C517's operating frequency, which is therefore specified at 1 MHz. Since the frequency comparator of the oscillator watchdog takes its inputs directly from the on-chip oscillator, the minimum frequency of 1 MHz does not restrict the use of the slow-down mode. In this mode the CPU runs with one eighth of the normal clock rate (see section 7.7). The oscillator watchdog circuitry can be enabled externally. lf the OWE pin (oscillator watchdog enable) is pulled low, the oscillator watchdog function is off. lf the pin is left unconnected or has a logic high level, the watchdog oscillator is activated. Thus, the watchdog is enabled even if the pin or the path to the pin is broken. Like the watchdog timer circuitry, the oscillator watchdog circuitry contains a status flip-flop. This flip-flop is set when an oscillator failure is detected and it is cleared by an external HW reset or by software (see figure 7-62). The block diagram in figure 7-64 illustrates the function of the oscillator watchdog. Note that the OWD reset request is held for at least three additional cycles after the on-chip oscillator returns to normal operation. This is done to ensure a proper oscillator startup.
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On-Chip Peripheral Components
Figure 7-64 Functional Block Diagram of the Oscillator Watchdog
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7.9
Oscillator and Clock Circuit
XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip at half the oscillator frequency. These signals define the internal phases, states and machine cycles, as described in chapter 3. Figure 7-65 shows the recommended oscillator circuit.
Figure 7-65 Recommended Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 7-66). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 30 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. lt a ceramic resonator is used, C1 and C2 are normally selected to be of somewhat higher values, typically 47 pF. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors.
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On-Chip Peripheral Components
To drive the SAB 80 C517 with an external clock source, the external clock signal is to be applied to XTAL2, as shown in figure 7-67. XTAL1 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL2.
Figure 7-66 On-Chip Oscillator Circuitry
Figure 7-67 External Clock Source
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7.10
System Clock Output
For peripheral devices requiring a system clock, the SAB 80C517 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON0, see figure 7-68), a clock signal with 1/12 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1), which is also the default after reset.
Figure 7-68 Special Function Register ADCON0 (Address 0D8H) 0DFH 0D8H BD 0DEH CLK 0DDH ADEX 0DCH BSY 0DBH ADM 0DAH MX2 0D9H MX1 0D8H MX0 ADCON0
These bits are not used in controlling the clock out functions.
Bit CLK
Function Clockout enable bit. When set, pin P1.6/CLKOUT outputs the system clock which is 1/12 of the oscillator frequency.
The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing diagram of the system clock output is shown in figure 7-69. Note: During slow-down operation (see section 7.7) the frequency of the clockout signal is divided by eight.
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On-Chip Peripheral Components
Figure 7-69 Timing Diagram - System Clock Output
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Interrupt System
8
Interrupt System
The SAB 80C517 provides 14 interrupt sources with four priority levels. Seven interrupts can be generated by the on-chip peripherals (i.e. timer 0, timer 1, timer 2, compare timer, serial interfaces 0 and 1 and A/D converter), and seven interrupts may be triggered externally. Short Description of the Interrupt Structure for Advanced SAB 80(C)515 Users The interrupt structure of the SAB 80C517 has been mainly adapted from the SAB 80(C)515. Thus, each interrupt source has its dedicated interrupt vector and can be enabled/disabled individually; there are also four priority levels available. In the SAB 80C517 two interrupt sources have been added: - Compare timer overflow interrupt - Receive and transmit interrupt of serial interface 1 In the SAB 80(C)515 the 12 interrupt sources are combined to six pairs; each pair can be programmed to one of the four interrupt priority levels. In the SAB 80C517 the new interrupt sources were added to two of these pairs, thus forming triplets; therefore, the 14 interrupt sources are combined to six pairs or triplets; each pair or triplet can be programmed to one of the four interrupt priority levels (see chapter 8.2) Figure 8-1 gives a general overview of the interrupt sources and illustrates the request and control flags described in the next sections. The priority structure and the corresponding control bits are listed in section 8.2. 8.1 Interrupt Structure
A common mechanism is used to generate the various interrupts, each source having its own request flag(s) located in a special function register (e.g. TCON, IRCON, S0CON, S1CON). Provided the peripheral or external source meets the condition for an interrupt, the dedicated request flag is set, whether an interrupt is enabled or not. For example, each timer 0 overflow sets the corresponding request flag TF0. lf it is already set, it retains a one (1). But the interrupt is not necessarily serviced. Now each interrupt requested by the corresponding flag can individually be enabled or disabled by the enable bits in SFR's IEN0, IEN1, IEN2 (see figure 8-2, 8-3 and 8-4). This determines whether the interrupt will actually be performed. In addition, there is a global enable bit for all interrupts which, when cleared, disables all interrupts independent of their individual enable bits.
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Interrupt System
Figure 8-1 a) Interrupt Structure of the SAB 80C517 Semiconductor Group 153
Interrupt System
Figure 8-1 b) Interrupt Structure of the SAB 80C517 (cont'd)
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Interrupt System
Figure 8-2 Special Function Register IEN0 (Address 0A8H) 0AFH 0A8H EAL 0AEH WDT 0ADH ET2 0ACH ES0 0ABH ET1 0AAH EX1 0A9H ET0 0A8H EX0 IEN0
This bit is not used for interrupt control.
Bit EX0 ET0 EX1 ET1 ES0 ET2 EAL
Function Enables or disables external interrupt 0. If EX0 = 0, external interrupt 0 is disabled. Enables or disables the timer 0 overflow interrupt. If ET0 = 0, the timer 0 interrupt is disabled. Enables or disables external interrupt 1. If EX1 = 0, external interrupt 1 is disabled. Enables or disables the timer 1 overflow interrupt. If ET1 = 0, the timer 1 interrupt is disabled. Enables or disables the serial channel 0 interrupt. If ES0 = 0, the serial channel 0 interrupt is disabled. Enables or disables the timer 2 overflow or external reload interrupt. If ET2 = 0, the timer 2 interrupt is disabled. Enables or disables all interrupts. If EAL = 0, no interrupt will be acknowledged. If EAL = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
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Figure 8-3 Special Function Register IEN1 (Address 0B8H) 0BFH 0BEH 0BDH EX6 0BCH EX5 0BBH EX4 0BAH EX3 0B9H EX2 0B8H EADC IEN1
0B8H EXEN2 SWDT
This bit is not used for interrupt control.
Bit EADC EX2 EX3 EX4 EX5 EX6 EXEN2
Function Enables or disables the A/D converter interrupt. If EADC = 0, the A/D converter interrupt is disabled. Enables or disables external interrupt 2/capture/compare interrupt 4. If EX2 = 0, external interrupt 2 is disabled. Enables or disables external interrupt 3/capture/compare interrupt 0. If EX3 = 0, external interrupt 3 is disabled. Enables or disables external interrupt 4/capture/compare interrupt 1. If EX4 = 0, external interrupt 4 is disabled. Enables or disables external interrupt 5/capture/compare interrupt 2. If EX5 = 0, external interrupt 5 is disabled. Enables or disables external interrupt 6/capture/compare interrupt 3. If EX6 = 0, external interrupt 6 is disabled. Exables or disables the timer 2 external reload interrupt. EXEN2 = 0 disables the timer 2 external reload interrupt. The external reload function is not affected by EXEN2.
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Figure 8-4 Special Function Register IEN2 (Address 09AH) 09AH - - - - ECT - - ES1 IEN2
Bit ES1 ECT
Function Enable serial interrupt of interface 1. Enables or disables the interrupt of serial interface 1. If ES1 = 0, the interrupt is disabled. Enable compare timer interrupt. Enables or disables the interrupt at compare timer overflow. If ECT = 0, the interrupt is disabled.
In the following the interrupt sources are discussed individually. The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative transition-activated, depending on bits IT0 and IT1 in register TCON (see figure 8-5). The flags that actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to, but only if the interrupt was transition-activated. lf the interrupt was level-activated, then the requesting external source directly controls the request flag, rather than the on-chip hardware. The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set by a rollover in their respective timer/counter registers (exception see section 7.3.4 for timer 0 in mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored too. The two interrupts of the serial interfaces are generated by the request flags RI0 and TI0 (in register S0CON) or Rl1 and Tl1 (in register S1CON), respectively. Figures 7-7 and 7-12 show SFR's S0CON and S1CON. That is, the two request flags of each serial interface are logically ORed together. Neither of these flags is cleared by hardware when the service routine is vectored too. In fact, the service routine of each interface will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, and the bit will have to be cleared by software. The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in register IRCON. Figures 8-6 and 8-7 show SFR's T2CON and IRCON. Neither of these flags is cleared by hardware when the service routine is vectored too. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software.
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Figure 8-5 Special Function Register TCON (Address 88H) 8FH 88H TF1 8EH TR1 8DH TF0 8CH TR0 8BH IE1 8AH IT1 89H IE0 88H IT0 TCON
These bits are not used for interrupt control.
Bit IT0 IE0 IT1 IE1 TF0 TF1
Function Interrupt 0 type control bit. Set/cleared by software to specify falling edge/lowlevel triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt is initiated. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/lowlevel triggered external interrupts. Interrupt 1 edge flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt is initiated. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when interrupt is initiated. Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when interrupt is initiated.
The A/D converter interrupt is generated by IADC in register IRCON (see figure 8-7). lt is set some cycles before the result is available. That is, if an interrupt is generated, in any case the converted result in ADDAT is valid on the first instruction of the interrupt service routine (with respect to the minimal interrupt response time). lf continuous conversions are established, IADC is set once during each conversion. lf an A/D converter interrupt is generated, flag IADC will have to be cleared by software. The external interrupt 2 (INT2/CC4) can be either positive or negative transition-activated depending on bit I2FR in register T2CON (see figure 8-6). The flag that actually generates this interrupt is bit IEX2 in register IRCON. In addition, this flag will be set if a compare event occurs at the corresponding output pin P1.4/INT2/CC4, regardless of the compare mode established and the transition at the respective pin. lf an interrupt 2 is generated, flag IEX2 is cleared by hardware when the service routine is vectored too.
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Interrupt System
Figure 8-6 Special Function Register T2CON (Address 0C8H) 0CFH 0C8H T2PS 0CEH I3FR 0CDH I2FR 0CCH T2R1 0CBH T2R0 0CAH T2CM 0C9H T2I1 0C8H T2I0 T2CON
These bits are not used for interrupt control.
Bit I2FR
Function External interrupt 2 falling/rising edge flag. When set, the interrupt 2 request flag IEX2 will be set on a positive transition at pin P1.4/INT2. I2FR = 0 specifies external interrupt 2 to be negative-transition activated. External interrupt 3 falling/rising edge flag. When set, the interrupt 3 request flag IEX3 will be set on a positive transition at pin P1.0/INT3. I3FR = 0 specifies external interrupt 3 to be negative-transition active.
I3FR
Like the external interrupt 2, the external interrupt 3 can be either positive or negative transitionactivated, depending on bit I3FR in register T2CON. The flag that actually generates this interrupt is bit IEX3 in register IRCON. In addition, this flag will be set if a compare event occurs at pin P1.0/INT3/CC0, regardless of the compare mode established and the transition at the respective pin. The flag IEX3 is cleared by hardware when the service routine is vectored too. The external interrupts 4 (INT4), 5 (INT5), 6 (INT6) are positive transition-activated. The flags that actually generate these interrupts are bits IEX4, IEX5, and IEX6 in register IRCON (see figure 8-7). In addition, these flags will be set if a compare event occurs at the corresponding output pin P1.1/INT4/CC1, P1.2/INT5/CC2, and P1.3/INT6/CC3, regardless of the compare mode established and the transition at the respective pin. When an interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored too. The compare timer interrupt is generated by bit CTF in register CTCON (see figure 8-8), which is set by a rollover in the compare timer. lf a compare timer interrupt is generated, flag CTF will have to be cleared by software.
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Interrupt System
Figure 8-7 Special Function Register IRCON (Address 0C0H) 0C7H 0C0H EXF2 0C6H TF2 0C5H IEX6 0C4H IEX5 0C3H IEX4 0C2H IEX3 0C1H IEX2 0C0H IADC IRCON
Bit IADC IEX2
Function A/D converter interrupt request flag. Set by hardware at the end of a conversion. Must be cleared by software. External interrupt 2 edge flag. Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1.4/INT2/CC4. Cleared when interrupt is initiated. External interrupt 3 edge flag. Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1.0/INT3/CC0. Cleared when interrupt is initiated. External interrupt 4 edge flag. Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1.1/INT4/CC1. Cleared when interrupt is initiated. External interrupt 5 edge flag. Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1.2/INT5/CC2. Cleared when interrupt is initiated. External interrupt 6 edge flag. Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1.3/INT6/CC3. Cleared when interrupt is initiated. Timer 2 overflow flag. Set by timer 2 overflow. Must be cleared by software. If the timer 2 interrupt is enabled, TF2 = 1 will cause an interrupt. Timer 2 external reload flag. Set when a reload is caused by a negative transition on pin T2EX while EXEN2 = 1. When the timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector the timer 2 interrupt routine. Can be used as an additional external interrupt when the reload function is not used. EXF2 must be cleared by software.
IEX3
IEX4
IEX5
IEX6
TF2 EXF2
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Figure 8-8 Special Function Register CTCON (Address 0E1H) 0E1H T2PS1 1) - - - CTF CLK2 CLK1 CLK0 CTCON
These bits are not used for interrupt control.
Bit CTF
Function Compare timer overflow. Set by hardware at a rollover of the compare timer. Bit is cleared by hardware (since CA-step; cleared by software in BC-step and earlier versions). If the compare timer interrupt is enabled. CTF = 1 will cause an interrupt.
All of these bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The only exceptions are the request flags IE0 and lE1. lf the external interrupts 0 and 1 are programmed to be level-activated, IE0 and lE1 are controlled by the external source via pin INT0 and INT1, respectively. Thus, writing a one to these bits will not set the request flag IE0 and/or lE1. In this mode, interrupts 0 and 1 can only be generated by software and by writing a 0 to the corresponding pins INT0 (P3.2) and INT1 (P3.3), provided that this will not affect any peripheral circuit connected to the pins. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in the special function registers IEN0, IEN1 and IEN2 (figures 8-2, 8-3 and 8-4). Note that IEN0 contains also a global disable bit, EAL, which disables all interrupts at once. Also note that in the SAB 8051 the interrupt priority register IP is located at address 0B8H; in the SAB 80C517 this location is occupied by register IEN1.
1) Only available in SAB 80C517 identification mark 'BB' or later.
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8.2
Priority Level Structure
As already mentioned above, all interrupt sources are combined as pairs or triplets; table 8-1 lists the structure of the interrupt sources.
Table 8-1 Pairs and Triplets of Interrupt Sources External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Timer 2 interrupt Serial channel 1 interrupt - - Compare timer interrupt - - A/D converter interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6
Each pair or triplet of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1 (figure 8-9). A lowpriority interrupt can itself be interrupted by a high-priority interrupt, but not by another interrupt of the same or a lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt source. lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. Thus, within each priority level there is a second priority structure determined by the polling sequence, as follows (see figure 8-10): - Within one pair or triplet the leftmost interrupt is serviced first, then the second and third, when available. - The pairs or triplets are serviced from top to bottom of the table.
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Figure 8-9 Special Function Registers IP0 and IP1 (Address 0A9H and 0B9H) 0A9H OWDS WDTS 0B9H - - IP0.5 IP1.5 IP0.4 IP1.4 IP0.3 IP1.3 IP0.2 IP1.2 IP0.1 IP1.1 IP0.0 IP1.0 IP0 IP1
These bits are not used for interrupt control. Corresponding bit locations in both registers are used to set the interrupt priority level of an interrupt pair or triplet. Bit IP1.x 0 0 1 1 Bit IP1.0/IP0.0 IP1.1/IP0.1 IP1.2/IP0.2 IP1.3/IP0.3 IP1.4/IP0.4 IP1.5/IP0.5 0 1 0 1 Function IP0.x - Set priority level 0 (lowest) Set priority level 1 Set priority level 2 Set priority level 3 (highest) Function IE0/RI1 + TI1/IADC TF0/IEX2 IE1/IEX3 TF1/CTF/IEX4 RI0 + TI0/IEX5 TF2 + EXF2/IEX6
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Interrupt System
Figure 8-10 Priority-Within-Level Structure. High IE0 TF0 IE1 TF1 RI0 + TI0 TF2 + EXF2 Note: This "priority-within-level" structure is only used to resolve simultaneous requests of the same priority level. 8.3 How Interrupts are Handled Interrupt Source RI1+TI1 IADC IEX2 IEX3 IEX4 IEX5 IEX6 High Low Priority
CTF - -
Low
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. lf one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1) 2) 3) An interrupt of equal or higher priority is already in progress. The current (polling) cycle is not in the final cycle of the instruction in progress. The instruction in progress is RETI or any write access to registers IEN0, IEN1, IEN2 or IP0 and IP1.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IEN0, IEN1, IEN2 or IP0 and IP1, then at least one more instruction will be executed before any interrupt is vectored too; this delay guarantees that changes of the interrupt status can be observed by the CPU.
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The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests. The polling cycle/LCALL sequence is illustrated in figure 8-11.
C1 S5P2
C2
C3
C4
C5
Interrupt is latched
Interrupts are polled
Long Call to Interrupt Vector Address
Interrupt Routine
MCT01859
Figure 8-11 Interrupt Response Timing Diagram Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 8-11, then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed. Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, while in other cases it does not; then this has to be done by the user's software. The hardware clears the external interrupt flags IE0 and lE1 only if they were transition-activated. The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the program counter with an address that depends on the source of the interrupt being vectored too, as shown in the following (table 8-2).
Semiconductor Group
165
Interrupt System
Table 8-2 Interrupt Source and Vectors Interrupt Request Flags IE0 TF0 IE1 TF1 RI0/TI0 TF2/EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 RI1/TI1 CTF Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 0083H 009BH Interrupt Source External interrupt 0 Timer 0 overflow External interrupt 1 Timer 1 overflow Serial channel 0 Timer 2 overflow/ext. reload A/D converter External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Serial channel 1 Compare timer overflow
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the two top bytes from the stack and reloads the program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level. A simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of the same or lower priority level would be acknowledged.
Semiconductor Group
166
Interrupt System
8.4
External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition activated by setting or clearing bit IT0 or IT1, respectively, in register TCON (see figure 8-5). lf ITx = 0 (x = 0 or 1), external interrupt x is triggered by a detected low level at the INTx pin. lf ITx = 1, external interrupt x is negative edge-triggered. In this mode, if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag lEx in TCON is set. Flag bit lEx then requests the interrupt. lf the external interrupt 0 or 1 is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. The external interrupts 2 and 3 can be programmed to be negative or positive transition-activated by setting or clearing bit I2FR or I3FR in register T2CON (see figure 8-6). lf IxFR = 0 (x = 2 or 3), external interrupt x is negative transition-activated. lf IxFR = 1, external interrupt is triggered by a positive transition. The external interrupts 4, 5, and 6 are activated by a positive transition. The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1.5/T2EX but only if bit EXEN2 is set. Since the external interrupt pins (INT2 to INT6) are sampled once in each machine cycle, an input high or low should be held for at least 12 oscillator periods to ensure sampling. lf the external interrupt is transition-activated, the external source has to hold the request pin low (high for INT2 and INT3, if it is programmed to be negative transition-active) for at least one cycle, and then hold it high (low) for at least one cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set (see figure 8-12). The external interrupt request flags will automatically be cleared by the CPU when the service routine is called.
Semiconductor Group
167
Interrupt System
Figure 8-12 External Interrupt Detection 8.5 Response Time
lf an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. lf the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request was blocked by one of the three previously listed conditions. lf an interrupt of equal or higher priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. lf the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles since the longest instructions (MUL and DIV) are only 4 cycles long; and, if the instruction in progress is RETI or a write access to registers IEN0, IEN1, IEN2 or IP0, IP1, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction, if the instruction is MUL or DIV). Thus, in a single interrupt system, the response time is always more than 3 cycles and less than 9 cycles.
Semiconductor Group
168
Instruction Set
9
Instruction Set
The SAB 80C517 instruction set includes 111 instructions, 49 of which are single-byte, 45 two-byte and 17 three-byte instructions. The instruction opcode format consists of a function mnemonic followed by a "destination, source" operand field. This field specifies the data type and addressing method(s) to be used. Like all other members of the 8051-family, the SAB 80C517 can be programmed with the same instruction set common to the basic member, the SAB 8051. Thus, the SAB 80C517 is 100% software compatible to the SAB 8051 and may be programmed with 8051 assembler or high-level languages. 9.1 Addressing Modes
The SAB 80C517 uses five addressing modes: - - - - - register direct immediate register indirect base register plus index-register indirect
Table 9-1 summarizes the memory spaces which may be accessed by each of the addressing modes. Register Addressing Register addressing accesses the eight working registers (R0 - R7) of the selected register bank. The least significant bit of the instruction opcode indicates which register is to be used. ACC, B, DPTR and CY, the Boolean processor accumulator, can also be addressed as registers. Direct Addressing Direct addressing is the only method of accessing the special function registers. The lower 128 bytes of internal RAM are also directly addressable. Immediate Addressing Immediate addressing allows constants to be part of the instruction in program memory.
Semiconductor Group
169
Instruction Set
Table 9-1 Addressing Modes and Associated Memory Spaces Addressing Modes Register addressing Direct addressing Immediate addressing Register indirect addressing Base register plus index register addressing Register Indirect Addressing Register indirect addressing uses the contents of either R0 or R1 (in the selected register bank) as a pointer to locations in a 256-byte block: the 256 bytes of internal RAM or the lower 256 bytes of external data memory. Note that the special function registers are not accessible by this method. The upper half of the internal RAM can be accessed by indirect addressing only. Access to the full 64 Kbytes of external data memory address space is accomplished by using the 16-bit data pointer. Execution of PUSH and POP instructions also uses register indirect addressing. The stack may reside anywhere in the internal RAM. Base Register plus Index Register Addressing Base register plus index register addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (DPTR or PC) and index register, ACC. This mode facilitates look-up table accesses. Boolean Processor The Boolean processor is a bit processor integrated into the SAB 80C517. It has its own instruction set, accumulator (the carry flag), bit-addressable RAM and l/O. Associated Memory Spaces R0 through R7 of selected register bank, ACC, B, CY (Bit), DPTR Lower 128 bytes of internal RAM, special function registers Program memory Internal RAM (@R1, @R0, SP), external data memory (@R1, @R0, @DPTR) Program memory (@DPTR + A, @PC + A)
Semiconductor Group
170
Instruction Set
The Bit Manipulation Instructions Allow: - - - - - - - set bit clear bit complement bit jump if bit is set jump if bit is not set jump if bit is set and clear bit move bit from / to carry
Addressable bits, or their complements, may be logically AND-ed or OR-ed with the contents of the carry flag. The result is returned to the carry register. 9.2 Introduction to the Instruction Set
The instruction set is divided into four functional groups: - - - - 9.2.1 data transfer arithmetic logic control transfer Data Transfer
Data operations are divided into three classes: - general-purpose - accumulator-specific - address-object None of these operations affects the PSW flag settings except a POP or MOV directly to the PSW.
Semiconductor Group
171
Instruction Set
General-Purpose Transfers - MOV performs a bit or byte transfer from the source operand to the destination operand. - PUSH increments the SP register and then transfers a byte from the source operand to the stack location currently addressed by SP. - POP transfers a byte operand from the stack location addressed by the SP to the destination operand and then decrements SP. Accumulator-Specific Transfers - XCH exchanges the byte source operand with register A (accumulator). - XCHD exchanges the low-order nibble of the source operand byte with the low-order nibble of A. - MOVX performs a byte move between the external data memory and the accumulator. The external address can be specified by the DPTR register (16 bit) or the R1 or R0 register (8 bit). - MOVC moves a byte from program memory to the accumulator. The operand in A is used as an index into a 256-byte table pointed to by the base register (DPTR or PC). The byte operand accessed is transferred to the accumulator. Address-Object Transfer - MOV DPTR, #data loads 16 bits of immediate data into a pair of destination registers, DPH and DPL. 9.2.2 Arithmetic
The SAB 80C517 has four basic mathematical operations. Only 8-bit operations using unsigned arithmetic are supported directly. The overflow flag, however, permits the addition and subtraction operation to serve for both unsigned and signed binary integers. Arithmetic can also be performed directly on packed BCD representations. Addition - INC (increment) adds one to the source operand and puts the result in the operand. - ADD adds A to the source operand and returns the result to A. - ADDC (add with carry) adds A and the source operand, then adds one (1) if CY is set, and puts the result in A. - DA (decimal-add-adjust for BCD addition) corrects the sum which results from the binary addition of two-digit decimal operands. The packed decimal sum formed by DA is returned to A. CY is set if the BCD result is greater than 99; otherwise, it is cleared.
Semiconductor Group
172
Instruction Set
Subtraction - SUBB (subtract with borrow) subtracts the second source operand from the the first operand (the accumulator), subtracts one (1) if CY is set and returns the result to A. - DEC (decrement) subtracts one (1) from the source operand and returns the result to the operand. Multiplication - MUL performs an unsigned multiplication of the A register, returning a double byte result. A receives the low-order byte, B receives the high-order byte. OV is cleared if the top half of the result is zero and is set if it is not zero. CY is cleared. AC is unaffected. Division - DIV performs an unsigned division of the A register by the B register; it returns the integer quotient to the A register and returns the fractional remainder to the B register. Division by zero leaves indeterminate data in registers A and B and sets OV; otherwise, OV is cleared. CY is cleared. AC remains unaffected. Flags Unless otherwise stated in the previous descriptions, the flags of PSW are affected as follows: - CY is set if the operation causes a carry to or a borrow from the resulting high-order bit; otherwise CY is cleared. - AC is set if the operation results in a carry from the low-order four bits of the result (during addition), or a borrow from the high-order bits to the low-order bits (during subtraction); otherwise AC is cleared. - OV is set if the operation results in a carry to the high-order bit of the result but not a carry from the bit, or vice versa; otherwise OV is cleared. OV is used in two's-complement arithmetic, because it is set when the signal result cannot be represented in 8 bits. - P is set if the modulo-2 sum of the eight bits in the accumulator is 1 (odd parity); otherwise P is cleared (even parity). When a value is written to the PSW register, the P bit remains unchanged, as it always reflects the parity of A.
Semiconductor Group
173
Instruction Set
9.2.3
Logic
The SAB 80C517 performs basic logic operations on both bit and byte operands. Single-Operand Operations - CLR sets A or any directly addressable bit to zero (0). - SETB sets any directly bit-addressable bit to one (1). - CPL is used to complement the contents of the A register without affecting any flag, or any directly addressable bit location. - RL, RLC, RR, RRC, SWAP are the five operations that can be performed on A. RL, rotate left, RR, rotate right, RLC, rotate left through carry, RRC, rotate right through carry, and SWAP, rotate left four. For RLC and RRC the CY flag becomes equal to the last bit rotated out. SWAP rotates A left four places to exchange bits 3 through 0 with bits 7 through 4. Two-Operand Operations - ANL performs bitwise logical AND of two operands (for both bit and byte operands) and returns the result to the location of the first operand. - ORL performs bitwise logical OR of two source operands (for both bit and byte operands) and returns the result to the location of the first operand. - XRL performs logical Exclusive OR of two source operands (byte operands) and returns the result to the location of the first operand. 9.2.4 Control Transfer
There are three classes of control transfer operations: unconditional calls, returns, jumps, conditional jumps, and interrupts. All control transfer operations, some upon a specific condition, cause the program execution to continue a non-sequential location in program memory.
Semiconductor Group
174
Instruction Set
Unconditional Calls, Returns and Jumps Unconditional calls, returns and jumps transfer control from the current value of the program counter to the target address. Both direct and indirect transfers are supported. - ACALL and LCALL push the address of the next instruction onto the stack and then transfer control to the target address. ACALL is a 2-byte instruction used when the target address is in the current 2K page. LCALL is a 3-byte instruction that addresses the full 64K program space. In ACALL, immediate data (i.e. an 11-bit address field) is concatenated to the five most significant bits of the PC (which is pointing to the next instruction). If ACALL is in the last 2 bytes of a 2K page then the call will be made to the next page since the PC will have been incremented to the next instruction prior to execution. - RET transfers control to the return address saved on the stack by a previous call operation and decrements the SP register by two (2) to adjust the SP for the popped address. - AJMP, LJMP and SJMP transfer control to the target operand. The operation of AJMP and LJMP are analogous to ACALL and LCALL. The SJMP (short jump) instruction provides for transfers within a 256-byte range centered about the starting address of the next instruction (- 128 to + 127). - JMP @A + DPTR performs a jump relative to the DPTR register. The operand in A is used as the offset (0 - 255) to the address in the DPTR register. Thus, the effective destination for a jump can be anywhere in the program memory space. Conditional Jumps Conditional jumps perform a jump contingent upon a specific condition. The destination will be within a 256-byte range centered about the starting address of the next instruction (- 128 to + 127). JZ performs a jump if the accumulator is zero. JNZ performs a jump if the accumulator is not zero. JC performs a jump if the carry flag is set. JNC performs a jump if the carry flag is not set. JB performs a jump if the directly addressed bit is set. JNB performs a jump if the directly addressed bit is not set. JBC performs a jump if the directly addressed bit is set and then clears the directly addressed bit. - CJNE compares the first operand to the second operand and performs a jump if they are not equal. CY is set if the first operand is less than the second operand; otherwise it is cleared. Comparisons can be made between A and directly addressable bytes in internal data memory or an immediate value and either A, a register in the selected register bank, or a register indirectly addressable byte of the internal RAM. - DJNZ decrements the source operand and returns the result to the operand. A jump is performed if the result is not zero. The source operand of the DJNZ instruction may be any directly addressable byte in the internal data memory. Either direct or register addressing may be used to address the source operand. Interrupt Returns - RETI transfers control as RET does, but additionally enables interrupts of the current priority level. - - - - - - -
Semiconductor Group
175
Instruction Set
9.3
Instruction Definitions
All 111 instructions of the SAB 80C517 can essentially be condensed to 54 basic operations, in the following alphabetically ordered according to the operation mnemonic section.
Instruction CY ADD ADDC SUBB MUL DIV DA RRC RLC CJNE X X X 0 0 X X X X
Flag OV X X X X X AC X X X
Instruction CY SETB C CLR C CPL C ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit 1 0 X X X X X X
Flag OV AC
A brief example of how the instruction might be used is given as well as its effect on the PSW flags. The number of bytes and machine cycles required, the binary machine language encoding, and a symbolic description or restatement of the function is also provided. Note: Only the carry, auxiliary carry, and overflow flags are discussed. The parity bit is computed after every instruction cycle that alters the accumulator. Similarily, instructions which alter directly addressed registers could affect the other status flags if the instruction is applied to the PSW. Status flags can also be modified by bit manipulation.
Semiconductor Group
176
Instruction Set
Notes on Data Addressing Modes Rn direct @Ri #data #data 16 bit A Working register R0-R7 128 internal RAM locations, any l/O port, control or status register Indirect internal or external RAM location addressed by register R0 or R1 8-bit constant included in instruction 16-bit constant included as bytes 2 and 3 of instruction 128 software flags, any bit-addressable l/O pin, control or status bit Accumulator
Notes on Program Addressing Modes addr16 addr11 rel Destination address for LCALL and LJMP may be anywhere within the 64-Kbyte program memory address space. Destination address for ACALL and AJMP will be within the same 2-Kbyte page of program memory as the first byte of the following instruction. SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127/- 128 bytes relative to the first byte of the following instruction.
(c)
All mnemonics copyrighted:
Intel Corporation 1980
Semiconductor Group
177
Instruction Set
ACALL Function:
addr11 Absolute call ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, op code bits 7-5, and the second byte of the instruction. The subroutine called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL. No flags are affected. Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345H. After executing the instruction ACALL SUBRTN
Description:
Example:
at location 0123H, SP will contain 09H, internal RAM location 08H and 09H will contain 25H and 01H, respectively, and the PC will contain 0345H. Operation: ACALL (PC) (PC) + 2 (SP) (SP) + 1 ((SP)) (PC7-0) (SP) (SP) + 1 ((SP)) (PC15-8) (PC10-0) page address a10 a9 a8 1 2 2 0001 a7 a6 a5 a4 a3 a2 a1 a0
Encoding: Bytes: Cycles:
Semiconductor Group
178
Instruction Set
ADD Function:
A, Add ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, registerindirect, or immediate.
Description:
Example:
The accumulator holds 0C3 H (11000011B) and register 0 holds 0AAH (10101010B). The instruction ADD A,R0
will leave 6DH (01101101B) in the accumulator with the AC flag cleared and both the carry flag and OV set to 1. ADD Operation: A,Rn ADD (A) (A) + (Rn) 0010 1 1 A,direct ADD (A) (A) + (direct) 0001 2 1 0101 direct address 1rrr
Encoding: Bytes: Cycles: ADD Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
179
Instruction Set
ADD Operation:
A, @Ri ADD (A) (A) + ((Ri)) 0010 1 1 A, #data ADD (A) (A) + #data 0010 2 1 0100 immediate data 011i
Encoding: Bytes: Cycles: ADD Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
180
Instruction Set
ADDC Function:
A, < src-byte> Add with carry ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, registerindirect, or immediate.
Description:
Example:
The accumulator holds 0C3 H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The instruction ADDC A,R0
will leave 6EH (01101110B) in the accumulator with AC cleared and both the carry flag and OV set to 1. ADDC Operation: A,Rn ADDC (A) (A) + (C) + (Rn) 0011 1 1 A,direct ADDC (A) (A) + (C) + (direct) 0011 2 1 0101 direct address 1rrr
Encoding: Bytes: Cycles: ADDC Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
181
Instruction Set
ADDC Operation:
A, @Ri ADDC (A) (A) + (C) + ((Ri)) 0011 1 1 A, #data ADDC (A) (A) + (C) + #data 0011 2 1 0100 immediate data 011i
Encoding: Bytes: Cycles: ADDC Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
182
Instruction Set
AJMP Function:
addr11 Absolute jump AJMP transfers program execution to the indicated address, which is formed at runtime by concatenating the high-order five bits of the PC (after incrementing the PC twice), op code bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP. The label "JMPADR" is at program memory location 0123H. The instruction AJMP JMPADR is at location 0345H and will load the PC with 0123H.
Description:
Example:
Operation:
AJM P (PC) (PC) + 2 (PC10-0) page address a10 a9 a8 0 2 2 0001 a7 a6 a5 a4 a3 a2 a1 a0
Encoding: Bytes: Cycles:
Semiconductor Group
183
Instruction Set
ANL Function:

, Logical AND for byte variables ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is a accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Description:
Example:
If the accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) then the instruction ANL A,R0 will leave 81H (10000001B) in the accumulator. When the destination is a directly addressed byte, this instruction will clear combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accumulator at run-time. The instruction ANL P1, #01110011B
will clear bits 7, 3, and 2 of output port 1. ANL Operation: A,Rn ANL (A) (A) (Rn) 0101 1 1 A,direct ANL (A) (A) (direct) 0101 2 1 184 0101 direct address 1rrr
Encoding: Bytes: Cycles: ANL Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
Instruction Set
ANL Operation:
A, @Ri ANL (A) (A) ((Ri)) 0101 1 1 A, #data ANL (A) (A) #data 0101 2 1 direct,A ANL (direct) (direct) (A) 0101 2 1 0101 direct address 0100 immediate data 011i
Encoding: Bytes: Cycles: ANL Operation:
Encoding: Bytes: Cycles: ANL Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
185
Instruction Set
ANL Operation:
direct, #data ANL (direct) (direct) #data 0101 3 2 0011 direct address immediate data
Encoding: Bytes: Cycles:
Semiconductor Group
186
Instruction Set
ANL Function:
C, Logical AND for bit variables If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash ("/" preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct bit addressing is allowed for the source operand.
Description:
Example:
Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0: MOV ANL ANL C,P1.0 C,ACC.7 C,/OV ; Load carry with input pin state ; AND carry with accumulator bit 7 ; AND with inverse of overflow flag
ANL Operation:
C,bit ANL (C) (C) (bit) 1000 2 2 C,/bit ANL (C) (C) / (bit) 1011 2 2 0000 bit address 0010 bit address
Encoding: Bytes: Cycles: ANL Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
187
Instruction Set
CJNE Function:

, < src-byte >, rel Compare and jump if not equal CJNE compares the magnitudes of the tirst two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cleared. Neither operand is affected. The first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.
Description:
Example:
The accumulator contains 34 H. Register 7 contains 56H. The first instruction in the sequence ; NOT_EQ ; CJNE ... JC ... R7, # 60H, NOT_EQ ..... REQ_LOW ..... ; R7 = 60H ; If R7 < 60H ; R7 > 60H
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H. If the data being presented to port 1 is also 34 H, then the instruction WAIT: CJNE A,P1,WAIT clears the carry flag and continues with the next instruction in sequence, since the accumulator does equal the data read from P1. (If some other value was input on P1, the program will loop at this point until the P1 data changes to 34 H).
Semiconductor Group
188
Instruction Set
CJNE Operation:
A,direct,rel (PC) (PC) + 3 if (A) < > (direct) then (PC) (PC) + relative offset if (A) < (direct) then (C) 1 else (C) 0 1011 3 2 A, #data,rel (PC) (PC) + 3 if (A) < > data then (PC) (PC) + relative offset if (A) data then (C) 1 else (C) 0 1011 3 2 RN, #data, rel (PC) (PC) + 3 if (Rn) < > data then (PC) (PC) + relative offset if (Rn) < data then (C) 1 else (C) 0 1011 3 2 1rrr immediate data rel. address 0100 immediate data rel. address 0101 direct address rel. address
Encoding: Bytes: Cycles: CJNE Operation:
Encoding: Bytes: Cycles: CJNE Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
189
Instruction Set
CJNE Operation:
@Ri, #data,rel (PC) (PC) + 3 if ((Ri)) < > data then (PC) (PC) + relative offset if ((Ri)) < data then (C) 1 else (C) 0 1011 3 2 011i immediate data rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
190
Instruction Set
CLR Function:
A Clear accumulator The accumulator is cleared (all bits set to zero). No flags are affected. The accumulator contains 5CH (01011100B). The instruction CLR A will leave the accumulator set to 00H (00000000B).
Description: Example:
Operation:
CLR (A) 0 1110 1 1 0100
Encoding: Bytes: Cycles:
Semiconductor Group
191
Instruction Set
CLR Function:
bit Clear bit The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Port 1 has previously been written with 5D H (01011101B). The instruction CLR P1.2 will leave the port set to 59H (01011001B).
Description: Example:
CLR Operation:
C CLR (C) 0 1100 1 1 bit CLR (bit) 0 1100 2 1 0010 bit address 0011
Encoding: Bytes: Cycles: CLR Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
192
Instruction Set
CPL Function:
A Complement accumulator Each bit of the accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to zero and vice versa. No flags are affected. The accumulator contains 5CH (01011100B). The instruction CPL A will leave the accumulator set to 0A3H (10100011B).
Description:
Example:
Operation:
CPL (A) / (A) 1111 1 1 0100
Encoding: Bytes: Cycles:
Semiconductor Group
193
Instruction Set
CPL Function:
bit Complement bit The bit variable specified is complemented. A bit which had been a one is changed to zero and vice versa. No other flags are affected. CPL can operate on the carry or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data will be read from the output data latch, not the input pin.
Description:
Example:
Port 1 has previously been written with 5DH (01011101B). The instruction sequence CPL CPL P1.1 P1.2
will leave the port set to 5BH (01011011B). CPL Operation: C CPL (bit) / (C) 1011 1 1 bit CPL (C) / (bit) 1011 2 1 0010 bit address 0011
Encoding: Bytes: Cycles: CPL Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
194
Instruction Set
DA Function:
A Decimal adjust accumulator for addition DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the accumulator producing the proper BCD digit in the loworder nibble. This internal addition would set the carry flag if a carry-out of the loworder four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carryout of the high-order bits, but wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially; this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the accumulator, depending on initial accumulator and PSW conditions. Note: DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation, nor does DA A apply to decimal subtraction.
Description:
Example:
The accumulator holds the value 56H (01010110B) representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (01100111B) representing the packed BCD digits of the decimal number 67. The carry flag is set. The instruction sequence ADDC DA A,R3 A
will first perform a standard two's-complement binary addition, resulting in the value 0BEH (10111110B) in the accumulator. The carry and auxiliary carry flags will be cleared. The decimal adjust instruction will then alter the accumulator to the value 24H (00100100B), indicating the packed BCD digits of the decimal number 24, the loworder two digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be set by the decimal adjust instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and 1 is 124.
Semiconductor Group
195
Instruction Set
BCD variables can be incremented or decremented by adding 01H or 99H. If the accumulator initially holds 30H (representing the digits of 30 decimal), then the instruction sequence ADD DA A, #99H A
will leave the carry set and 29H in the accumulator, since 30 + 99 = 129. The loworder byte of the sum can be interpreted to mean 30 - 1 = 29. Operation: DA contents of accumulator are BCD if [[(A3-0) > 9] [(AC) = 1]] then (A3-0) (A3-0) + 6 and if [[(A7-4) > 9] [(C) = 1]] then (A7-4) (A7-4) + 6 1101 1 1 0100
Encoding: Bytes: Cycles:
Semiconductor Group
196
Instruction Set
DEC Function:
byte Decrement The variable indicated is decremented by 1. An original value of 00H will underflow to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Description:
Example:
Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H and 40H, respectively. The instruction sequence DEC DEC DEC @R0 R0 @R0
will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH. DEC Operation: A DEC (A) (A) - 1 0001 1 1 Rn DEC (Rn) (Rn) - 1 0001 1 1 1rrr 0100
Encoding: Bytes: Cycles: DEC Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
197
Instruction Set
DEC Operation:
direct DEC (direct) (direct) - 1 0001 2 1 @Ri DEC ((Ri)) ((Ri)) - 1 0001 1 1 011i 0101 direct address
Encoding: Bytes: Cycles: DEC Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
198
Instruction Set
DIV Function:
AB Divide DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared.
Description:
Exception: If B had originally contained 00H, the values returned in the accumulator and B register will be undefined and the overflow flag will be set. The carry flag is cleared in any case.
Example: The accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). The instruction DIV AB will leave 13 in the accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13x18) + 17. Carry and OV will both be cleared. Operation: DIV (A15-8) (B7-0) (A) / (B)
Encoding: Bytes: Cycles:
1000 1 4
0100
Semiconductor Group
199
Instruction Set
DJNZ Function:
, < rel-addr> Decrement and jump if not zero DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H will underflow to 0FFH. No flags are affected. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Description:
Example:
Internal RAM locations 40H, 50H, and 60H contain the values, 01H, 70H, and 15H, respectively. The instruction sequence DJNZ 40H,LABEL_1 DJNZ 50H,LABEL_2 DJNZ 60H,LABEL_3 will cause a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in the three RAM locations. The first jump was not taken because the result was zero. This instruction provides a simple way of executing a program loop a given number of times, or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The instruction sequence MOV TOGGLE: CPL DJNZ R2, #8 P1.7 R2,TOGGLE
will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output port 1. Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
Semiconductor Group
200
Instruction Set
DJNZ Operation:
Rn,rel DJNZ (PC) (PC) + 2 (Rn) (Rn) - 1 if (Rn) > 0 or (Rn) < 0 then (PC) (PC) + rel 1101 2 2 direct,rel DJNZ (PC) (PC) + 2 (direct) (direct) - 1 if (direct) > 0 or (direct) < 0 then (PC) (PC) + rel 1101 3 2 0101 direct address rel. address 1rrr rel. address
Encoding: Bytes: Cycles: DJNZ Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
201
Instruction Set
INC Function:
Increment INC increments the indicated variable by 1. An original value of 0FF H will overflow to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Description:
Example:
Register 0 contains 7EH (01111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The instruction sequence INC INC INC @R0 R0 @R0
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) 00H and 41H. INC Operation: A INC (A) (A) + 1 0000 1 1 Rn INC (Rn) (Rn) + 1 0000 1 1 1rrr 0100
Encoding: Bytes: Cycles: INC Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
202
Instruction Set
INC Operation:
direct INC (direct) (direct) + 1 0000 2 1 @Ri INC ((Ri)) ((Ri)) + 1 0000 1 1 011i 0101 direct address
Encoding: Bytes: Cycles: INC Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
203
Instruction Set
INC Function:
DPTR Increment data pointer Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H will increment the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented.
Description:
Example:
Registers DPH and DPL contain 12H and 0FEH, respectively. The instruction sequence INC INC INC DPTR DPTR DPTR
will change DPH and DPL to 13H and 01H. Operation: INC (DPTR) (DPTR) + 1 1010 1 2 0011
Encoding: Bytes: Cycles:
Semiconductor Group
204
Instruction Set
JB Function:
bit,rel Jump if bit is set If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. The data present at input port 1 is 11001010 B. The accumulator holds 56 (01010110B). The instruction sequence JB JB P1.2,LABEL1 ACC.2,LABEL2
Description:
Example:
will cause program execution to branch to the instruction at label LABEL2. Operation: JB (PC) (PC) + 3 if (bit) = 1 then (PC) (PC) + rel 0010 3 2 0000 bit address rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
205
Instruction Set
JBC Function:
bit,rel Jump if bit is set and clear bit If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin.
Description:
Example:
The accumulator holds 56H (01010110B). The instruction sequence JBC JBC ACC.3,LABEL1 ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2, with the accumulator modified to 52H (01010010B). Operation: JBC (PC) (PC) + 3 if (bit) = 1 then (bit) 0 (PC) (PC) + rel 0001 3 2 0000 bit address rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
206
Instruction Set
JC Function:
rel Jump if carry is set If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relativedisplacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. The carry flag is cleared. The instruction sequence JC CPL JC LABEL1 C LABEL2
Description:
Example:
will set the carry and cause program execution to continue at the instruction identified by the label LABEL2. Operation: JC (PC) (PC) + 2 if (C) = 1 then (PC) (PC) + rel 0100 2 2 0000 rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
207
Instruction Set
JMP Function:
@A + DPTR Jump indirect Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the accumulator nor the data pointer is altered. No flags are affected. An even number from 0 to 6 is in the accumulator. The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP_TBL: MOV JMP JMP_TBL: AJMP AJMP AJMP AJMP DPTR, #JMP_TBL @A + DPTR LABEL0 LABEL1 LABEL2 LABEL3
Description:
Example:
If the accumulator equals 04 H when starting this sequence, execution will jump to label LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at every other address. Operation: JMP (PC) (A) + (DPTR) 0111 1 2 0011
Encoding: Bytes: Cycles:
Semiconductor Group
208
Instruction Set
JNB Function:
bit,rel Jump if bit is not set If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. The data present at input port 1 is 11001010 B. The accumulator holds 56H (01010110B). The instruction sequence JNB JNB P1.3,LABEL1 ACC.3,LABEL2
Description:
Example:
will cause program execution to continue at the instruction at label LABEL2. Operation: JNB (PC) (PC) + 3 if (bit) = 0 then (PC) (PC) + rel. 0011 3 2 0000 bit address rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
209
Instruction Set
JNC Function:
rel Jump if carry is not set If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. The carry flag is set. The instruction sequence JNC CPL JNC LABEL1 C LABEL2
Description:
Example:
will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2. Operation: JNC (PC) (PC) + 2 if (C) = 0 then (PC) (PC) + rel 0101 2 2 0000 rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
210
Instruction Set
JNZ Function:
rel Jump if accumulator is not zero If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified. No flags are affected. The accumulator originally holds 00H. The instruction sequence JNZ INC JNZ LABEL1 A LABEL2
Description:
Example:
will set the accumulator to 01H and continue at label LABEL2. Operation: JNZ (PC) (PC) + 2 if (A) 0 then (PC) (PC) + rel. 0111 2 2 0000 rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
211
Instruction Set
JZ Function:
rel Jump if accumulator is zero If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified. No flags are affected. The accumulator originally contains 01 H. The instruction sequence JZ DEC JZ LABEL1 A LABEL2
Description:
Example:
will change the accumulator to 00H and cause program execution to continue at the instruction identified by the label LABEL2. Operation: JZ (PC) (PC) + 2 if (A) = 0 then (PC) (PC) + rel 0110 2 2 0000 rel. address
Encoding: Bytes: Cycles:
Semiconductor Group
212
Instruction Set
LCALL Function:
addr16 Long call LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64 Kbyte program memory address space. No flags are affected. Initially the stack pointer equals 07H. The label "SUBRTN" is assigned to program memory location 1234H. After executing the instruction LCALL SUBRTN at location 0123H, the stack pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H.
Description:
Example:
Operation:
LCALL (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC7-0) (SP) (SP) + 1 ((SP)) (PC15-8) (PC) addr15-0 0001 3 2 0010 addr15 . . addr8 addr7 . . addr0
Encoding: Bytes: Cycles:
Semiconductor Group
213
Instruction Set
LJMP Function:
addr16 Long jump LJMP causes an unconditional branch to the indicated address, by loading the highorder and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected. The label "JMPADR" is assigned to the instruction at program memory location 1234H. The instruction LJMP JMPADR at location 0123H will load the program counter with 1234H.
Description:
Example:
Operation:
LJMP (PC) addr15-0 0000 3 2 0010 addr15 . . . addr8 addr7 . . . addr0
Encoding: Bytes: Cycles:
Semiconductor Group
214
Instruction Set
MOV Function:

, Move byte variable The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed.
Description:
Example:
Internal RAM location 30 H holds 40H. The value of RAM location 40 H is 10H. The data present at input port 1 is 11001010B (0CAH). MOV MOV MOV MOV MOV MOV R0, #30H A, @R0 R1,A B, @R1 @R1,P1 P2,P1 ; R0 < = 30H ; A < = 40H ; R1 < = 40H ; B < = 10H ; RAM (40H) < = 0CAH ; P2 < = 0CAH
leaves the value 30H in register 0, 40H in both the accumulator and register 1, 10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2. MOV Operation: A,Rn MOV (A) (Rn) 1110 1 1 A,direct *) MOV (A) (direct) 1110 2 1 0101 direct address 1rrr
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles:
*) MOV A,ACC is not a valid instruction. The content of the accumulator after the execution of this instruction is undefined.
Semiconductor Group
215
Instruction Set
MOV Operation:
A,@Ri MOV (A) ((Ri)) 1110 1 1 A, #data MOV (A) #data 0111 2 1 Rn,A MOV (Rn) (A) 1111 1 1 Rn,direct MOV (Rn) (direct) 1010 2 2 1rrr direct address 1rrr 0100 immediate data 011i
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
216
Instruction Set
MOV Operation:
Rn, #data MOV (Rn) #data 0111 2 1 direct,A MOV (direct) (A) 1111 2 1 direct,Rn MOV (direct) (Rn) 1000 2 2 direct,direct MOV (direct) (direct) 1000 3 2 0101 dir.addr. (src) dir.addr. (dest) 1rrr direct address 0101 direct address 1rrr immediate data
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
217
Instruction Set
MOV Operation:
direct, @ Ri MOV (direct) ((Ri)) 1000 2 2 direct, #data MOV (direct) #data 0111 3 2 @ Ri,A MOV ((Ri)) (A) 1111 1 1 @ Ri,direct MOV ((Ri)) (direct) 1010 2 2 011i direct address 011i 0101 direct address immediate data 011i direct address
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles: MOV Ooeration:
Encoding: Bytes: Cycles:
Semiconductor Group
218
Instruction Set
MOV Operation:
@ Ri,#data MOV ((Ri)) #data 0111 2 1 011i immediate data
Encoding: Bytes: Cycles:
Semiconductor Group
219
Instruction Set
MOV Function:

, Move bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected. The carry flag is originally set. The data present at input port 3 is 11000101 B. The data previously written to output port 1 is 35 H (00110101B). MOV MOV MOV P1.3,C C,P3.3 P1.2,C
Description:
Example:
will leave the carry cleared and change port 1 to 39H (00111001B). MOV Operation: C,bit MOV (C) (bit) 1010 2 1 bit,C MOV (bit) (C) 1001 2 2 0010 bit address 0010 bit address
Encoding: Bytes: Cycles: MOV Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
220
Instruction Set
MOV Function:
DPTR, #data16 Load data pointer with a 16-bit constant The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once.
Description:
Example:
The instruction MOV DPTR, #1234H
will load the value 1234H into the data pointer: DPH will hold 12H and DPL will hold 34H. Operation: MOV (DPTR) #data15-0 DPH DPL #data15-8 1001 3 2 0000
#data7-0 immed. data 15 . . . 8 immed. data 7 . . . 0
Encoding: Bytes: Cycles:
Semiconductor Group
221
Instruction Set
MOVC Function:
A, @A + Move code byte The MOVC instructions load the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added to the accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected. A value between 0 and 3 is in the accumulator. The following instructions will translate the value in the accumulator to one of four values defined by the DB (define byte) directive. REL_PC: INC MOVC RET DB DB DB DB A A, @A + PC 66H 77H 88H 99H
Description:
Example:
If the subroutine is called with the accumulator equal to 01H, it will return with 77H in the accumulator. The INC A before the MOVC instruction is needed to "get around" the RET instruction above the table. If several bytes of code separated the MOVC from the table, the corresponding number would be added to the accumulator instead. MOVC Operation: A, @A + DPTR MOVC (A) ((A) + (DPTR)) 1001 1 2 0 01 1
Encoding: Bytes: Cycles:
Semiconductor Group
222
Instruction Set
MOVC Operation:
A, @A + PC MOVC (PC) (PC) + 1 (A) ((A) + (PC)) 1000 1 2 0 01 1
Encoding: Bytes: Cycles:
Semiconductor Group
223
Instruction Set
MOVX Function:

, Move external The MOVX instructions transfer data between the accumulator and a byte of external data memory, hence the "X" appended to MOV. There are two types of instructions, differing in whether they provide an eight bit or sixteen-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provide an eight-bit address multiplexed with data on P0. Eight bits are sufficient for external l/O expansion decoding or a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins would be controlled by an output instruction preceding the MOVX. In the second type of MOVX instructions, the data pointer generates a sixteen-bit address. P2 outputs the high-order eight address bits (the contents of DPH) while P0 multiplexes the low-order eight bits (DPL) with data. The P2 special function register retains its previous contents while the P2 output buffers are emining the contents of DPH. This form is faster and more efficient when accessing very large data arrays (up to 64 Kbyte), since no additional instructions are needed to set up the output ports. It is possible in some situations to mix the two MOVX types. A large RAM array with its high-order address lines driven by P2 can be addressed via the data pointer, or with code to output high-order address bits to P2 followed by a MOVX instruction using R0 or R1.
Description:
Example:
An external 256-byte RAM using multiplexed address/data lines (e.g. an SAB 8155 RAM/I/O/timer) is connected to the SAB 80(c)5XX port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal l/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56 H. The instruction sequence MOVX MOVX A, @R1 @R0,A
copies the value 56H into both the accumulator and external RAM location 12H.
Semiconductor Group
224
Instruction Set
MOVX Operation:
A,@Ri MOVX (A) ((Ri)) 1110 1 2 A,@DPTR MOVX (A) ((DPTR)) 1110 1 2 @Ri,A MOVX ((Ri)) (A) 1111 1 2 @DPTR,A MOVX ((DPTR)) 1111 1 2 (A) 0000 001i 0000 001i
Encoding: Bytes: Cycles: MOVX Operation:
Encoding: Bytes: Cycles: MOVX Operation:
Encoding: Bytes: Cycles: MOVX Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
225
Instruction Set
MUL Function:
AB Multiply MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Originally the accumulator holds the value 80 (50H). Register B holds the value 160 (0A0H). The instruction MUL AB will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the accumulator is cleared. The overflow flag is set, carry is cleared.
Description:
Example:
Operation:
MUL (A7-0) (A) x (B) (B15-8)
Encoding: Bytes: Cycles:
1010 1 4
0100
Semiconductor Group
226
Instruction Set
NOP Function: Description: Example: No operation Execution continues at the following instruction. Other than the PC, no registers or flags are affected. It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles. A simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the instruction sequence CLR P2.7 NOP NOP NOP NOP SETB P2.7 Operation: Encoding: Bytes: Cycles: NOP 0000 1 1 0000
Semiconductor Group
227
Instruction Set
ORL Function:

Logical OR for byte variables ORL performs the bitwise logical OR operation between the indicated variables, storing the results in the destination byte. No flags are affected . The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Description:
Example:
If the accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the instruction ORL A,R0
will leave the accumulator holding the value 0D7H (11010111B). When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the accumulator at run-time. The instruction ORL P1,#00110010B
will set bits 5, 4, and 1 of output port 1. ORL Operation: A,Rn ORL (A) (A) (Rn) 0100 1 1 1rrr
Encoding: Bytes: Cycles:
Semiconductor Group
228
Instruction Set
ORL Operation:
A,direct ORL (A) (A) (direct) 0100 2 1 A,@Ri ORL (A) (A) ((Ri)) 0100 1 1 A,#data ORL (A) (A) #data 0100 2 1 direct,A ORL (direct) (direct) (A) 0100 2 1 0010 direct address 0100 immediate data 011i 0101 direct address
Encoding: Bytes: Cycles: ORL Operation:
Encoding: Bytes: Cycles: ORL Operation:
Encoding: Bytes: Cycles: ORL Operation:
Encoding: Bytes: Cycles:
Semiconductor Group
229
Instruction Set
ORL Operation:
direct, #data ORL (direct) (direct) #data 0100 3 2 0011 direct address immediate data
Encoding: Bytes: Cycles:
Semiconductor Group
230
Instruction Set
ORL Function:
C, Logical OR for bit variables Set the carry flag if the Boolean value is a logic 1; leave the carry in its current state otherwise. A slash ("/") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, or OV = 0: MOV ORL ORL C,P1.0 C,ACC.7 C,/OV ; Load carry with input pin P1.0 ; OR carry with the accumulator bit 7 ; OR carry with the inverse of OV
Description:
Example:
ORL Operation:
C,bit ORL (C) (C) (bit) 0111 2 2 C,/bit ORL (C) (C) / (bit) 1010 2 2 0000 bit address 0010 bit address
Encoding: Bytes: Cycles: ORL Operation:
Encoding: Bytes: Cycles:
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Instruction Set
POP Function:
direct Pop from stack The contents of the internal RAM location addressed by the stack pointer is read, and the stack pointer is decremented by one. The value read is the transfer to the directly addressed byte indicated. No flags are affected. The stack pointer originally contains the value 32 H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The instruction sequence POP POP DPH DPL
Description:
Example:
will leave the stack pointer equal to the value 30H and the data pointer set to 0123H. At this point the instruction POP SP
will leave the stack pointer set to 20H. Note that in this special case the stack pointer was decremented to 2FH before being loaded with the value popped (20H). Operation: POP (direct) ((SP)) (SP) (SP) - 1 1101 2 2 0000 direct address
Encoding: Bytes: Cycles:
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232
Instruction Set
PUSH Function:
direct Push onto stack The stack pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the stack pointer. Otherwise no flags are affected. On entering an interrupt routine the stack pointer contains 09H. The data pointer holds the value 0123H. The instruction sequence PUSH PUSH DPL DPH
Description:
Example:
will leave the stack pointer set to 0BH and store 23H and 01H in internal RAM locations 0AH and 0BH, respectively. Operation: PUSH (SP) (SP) + 1 ((SP)) (direct) 1100 2 2 0000 direct address
Encoding: Bytes: Cycles:
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233
Instruction Set
RET Function: Description: Return from subroutine RET pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected. The stack pointer originally contains the value 0B H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The instruction RET will leave the stack pointer equal to the value 09H. Program execution will continue at location 0123H. Operation: RET (PC15-8) ((SP)) (SP) (SP) - 1 (PC7-0) ((SP)) (SP) (SP) - 1 0010 1 2 0010
Example:
Encoding: Bytes: Cycles:
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Instruction Set
RETI Function: Description: Return from interrupt RETI pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower or same-level interrupt is pending when the RETI instruction is executed, that one instruction will be executed before the pending interrupt is processed. The stack pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The instruction RETI will leave the stack pointer equal to 09H and return program execution to location 0123H. RETI (PC15-8) ((SP)) (SP) (SP) - 1 (PC7-0) ((SP)) (SP) (SP) - 1 0011 1 2 0010
Example:
Operation:
Encoding: Bytes: Cycles:
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Instruction Set
RL Function:
A Rotate accumulator left The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. The accumulator holds the value 0C5H (11000101B). The instruction RL A leaves the accumulator holding the value 8BH (10001011B) with the carry unaffected.
Description: Example:
Operation:
RL (An + 1) (An) n = 0-6 (A0) (A7) 0010 1 1 0011
Encoding: Bytes: Cycles:
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Instruction Set
RLC Function:
A Rotate accumulator left through carry flag The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected. The accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction RLC A
Description:
Example:
leaves the accumulator holding the value 8AH (10001010B) with the carry set. Operation: RLC (An + 1) (An) n = 0-6 (A0) (C) (C) (A7) 0011 1 1 0011
Encoding: Bytes: Cycles:
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Instruction Set
RR Function:
A Rotate accumulator right The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. The accumulator holds the value 0C5H (11000101B). The instruction RR A leaves the accumulator holding the value 0E2H (11100010B) with the carry unaffected.
Description: Example:
Operation:
RR (An) (An + 1) n = 0-6 (A7) (A0) 0000 1 1 0011
Encoding: Bytes: Cycles:
Semiconductor Group
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Instruction Set
RRC Function:
A Rotate accumulator right through carry flag The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected. The accumulator holds the value 0C5H (11000101B), the carry is zero. The instruction RRC A
Description:
Example:
leaves the accumulator holding the value 62H (01100010B) with the carry set. Operation: RRC (An) (An + 1) n=0-6 (A7) (C) (C) (A0) 0001 1 1 0011
Encoding: Bytes: Cycles:
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Instruction Set
SETB Function:
Set bit SETB sets the indicated bit to one. SETB can operate on the carry flag or any directiy addressable bit. No other flags are affected. The carry flag is cleared. Output port 1 has been written with the value 34H (00110100B). The instructions SETB SETB C P1.0
Description: Example:
will leave the carry flag set to 1 and change the data output on port 1 to 35H (00110101B). SETB Operation: C SETB (C) 1 1101 1 1 bit SETB (bit) 1 1101 2 1 0010 bit address 0011
Encoding: Bytes: Cycles: SETB Operation:
Encoding: Bytes: Cycles:
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Instruction Set
SJMP Function:
rel Short jump Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it. The label "RELADR" is assigned to an instruction at program memory location 0123H. The instruction SJMP RELADR will assemble into location 0100H. After the instruction is executed, the PC will contain the value 0123H. Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore, the displacement byte of the instruction will be the relative offset (0123H0102H) = 21H. In other words, an SJMP with a displacement of 0FEH would be a one-instruction infinite loop.
Description:
Example:
Operation:
SJMP (PC) (PC) + 2 (PC) (PC) + rel 1000 2 2 0000 rel. address
Encoding: Bytes: Cycles:
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Instruction Set
SUBB Function:
A, Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source operand). AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7 but not bit 6. When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes: register, direct, registerindirect, or immediate.
Description:
Example:
The accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. The instruction SUBB A,R2
will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set. Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by a CLR C instruction. SUBB Operation: A,Rn SUBB (A) (A) - (C) - (Rn) 1001 1 1 1rrr
Encoding: Bytes: Cycles:
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Instruction Set
SUBB Operation:
A,direct SUBB (A) (A) - (C) - (direct) 1001 2 1 A, @ Ri SUBB (A) (A) - (C) - ((Ri)) 1001 1 1 A, #data SUBB (A) (A) - (C) - #data 1001 2 1 0100 immediate data 011i 0101 direct address
Encoding: Bytes: Cycles: SUBB Operation:
Encoding: Bytes: Cycles: SUBB Operation:
Encoding: Bytes: Cycles:
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Instruction Set
SWAP Function:
A Swap nibbles within the accumulator SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a fourbit rotate instruction. No flags are affected. The accumulator holds the value 0C5H (11000101B). The instruction SWAP A leaves the accumulator holding the value 5CH (01011100B).
Description:
Example:
Operation:
SWAP (A3-0) (A7-4), (A7-4) (A3-0) 1100 1 1 0100
Encoding: Bytes: Cycles:
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Instruction Set
XCH Function:
A, Exchange accumulator with byte variable XCH loads the accumulator with the contents of the indicated variable, at the same time writing the original accumulator contents to the indicated variable. The source/ destination operand can use register, direct, or register-indirect addressing. R0 contains the address 20H. The accumulator holds the value 3FH (00111111B). Internal RAM location 20H holds the value 75H (01110101B). The instruction XCH A, @R0 will leave RAM location 20H holding the value 3FH (00111111B) and 75H (01110101B) in the accumulator.
Description:
Example:
XCH Operation:
A,Rn XCH (A) (Rn) 1100 1 1 A,direct XCH (A) (direct) 1100 2 1 0101 direct address 1rrr
Encoding: Bytes: Cycles: XCH Operation:
Encoding: Bytes: Cycles:
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Instruction Set
XCH Operation:
A, @ Ri XCH (A) ((Ri)) 1100 1 1 011i
Encoding: Bytes: Cycles:
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246
Instruction Set
XCHD Function:
A,@Ri Exchange digit XCHD exchanges the low-order nibble of the accumulator (bits 3-0, generally representing a hexadecimal or BCD digit), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected. R0 contains the address 20H. The accumulator holds the value 36H (00110110B). Internal RAM location 20H holds the value 75H (01110101B). The instruction XCHD A, @ R0 will leave RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the accumulator.
Description:
Example:
Operation:
XCHD (A3-0)

((Ri)3-0) 011i
Encoding: Bytes: Cycles:
1101 1 1
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Instruction Set
XRL Function:

, Logical Exclusive OR for byte variables XRL performs the bitwise logical Exclusive OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Description:
Example:
If the accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) then the instruction XRL A,R0
will leave the accumulator holding the value 69H (01101001B). When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the accumulator at run-time. The instruction XRL P1,#00110001B
will complement bits 5, 4, and 0 of output port 1. XRL Operation: A,Rn XRL2 (A) (A) v (Rn) 0110 1 1 1rrr
Encoding: Bytes: Cycles:
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Instruction Set
XRL Operation:
A,direct XRL (A) (A) v (direct) 0110 2 1 A, @ Ri XRL (A) (A) v ((Ri)) 0110 1 1 A, #data XRL (A) (A) v #data 0110 2 1 direct,A XRL (direct) (direct) v (A) 0110 2 1 0010 direct address 0100 immediate data 011i 0101 direct address
Encoding: Bytes: Cycles: XRL Operation:
Encoding: Bytes: Cycles: XRL Operation:
Encoding: Bytes: Cycles: XRL Operation:
Encoding: Bytes: Cycles:
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Instruction Set
XRL Operation:
direct, #data XRL (direct) (direct) v #data 0110 3 2 0011 direct address immediate data
Encoding: Bytes: Cycles:
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250
Instruction Set
Instruction Set Summary Mnemonic Arithmetic Operations ADD ADD ADD ADD A,Rn A,direct A, @Ri A,#data Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust accumulator 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 Description Byte Cycle
ADDC A,Rn ADDC A,direct ADDC A, @Ri ADDC A, #data SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rn A,direct A,@Ri A,#data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A
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Instruction Set
Instruction Set Summary (cont'd) Mnemonic Logic Operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A direct A,@Ri A,#data direct,A direct,#data A A A A A A AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive OR register to accumulator Exclusive OR direct byte to accumulator Exclusive OR indirect RAM to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte Exclusive OR immediate data to direct byte Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 Description Byte Cycle
SWAP A
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Instruction Set
Instruction Set Summary (cont'd) Mnemonic Data Transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV A,Rn A,direct A,@Ri A,#data Rn,A Rn,direct Rn,#data direct,A direct,Rn direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri, #data
1)
Description
Byte
Cycle
Move register to accumulator Move direct byte to accumulator Move indirect RAM to accumulator Move immediate data to accumulator Move accumulator to register Move direct byte to register Move immediate data to register Move accumulator to direct byte Move register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate data to direct byte Move accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Move code byte relative to DPTR to accumulator Move code byte relative to PC to accumulator Move external RAM (8-bit addr.) to A Move external RAM (16-bit addr.) to A Move A to external RAM (8-bit addr.) Move A to external RAM (16-bit addr.) Push direct byte onto stack Pop direct byte from stack Exchange register with accumulator Exchange direct byte with accumulator Exchange indirect RAM with accumulator Exchange low-order nibble indir. RAM with A
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
DPTR, #data16 Load data pointer with a 16-bit constant
MOVC A,@A + DPTR MOVC A,@A + PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH direct POP XCH XCH XCH direct A,Rn A,direct A,@Ri
XCHD A,@Ri
1)
MOV A,ACC is not a valid instruction
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Instruction Set
Instruction Set Summary (cont'd) Mnemonic Description Byte Cycle
Boolean Variable Manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2
Program and Machine Control ACALL addr11 LCALL addr16 RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE addr11 addr16 rel @A + DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long iump Short jump (relative addr.) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct byte to A and jump if not equal 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
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Instruction Set
Instruction Set Summary (cont'd) Mnemonic Description Byte Cycle
Program and Machine Control (cont'd) CJNE CJNE CJNE DJNZ DJNZ NOP A,#data,rel Rn,#data rel @Ri,#data,rel Rn,rel direct,rel Compare immediate to A and jump if not equal Compare immed. to reg. and jump if not equal Compare immed. to ind. and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation 3 3 3 2 3 1 2 2 2 2 2 1
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Application Examples
10 10.1
Application Examples Application Examples for the Compare Functions
10.1.1 Generation of Two Different PWM Signals with "Additive Compare" using the "CCx Registers" The following example gives an idea of how to use compare mode 1 and compare interrupts for an "additive pulse width modulation". Assume that an application requires two PWM signals at two port pins providing different switching frequencies, e.g. a switching frequency of 2 kHz at port 1.1 (further on called PWM channel 1) and 5 kHz at port 1.2 (further on called PWM channel 2). In this case compare mode 0 cannot be used since it uses the timer overflow signal to switch all compare outputs to low level and thereby provides the same switching frequency. In our case, ^ however, the period of each PWM signal is different, being 0.5 ms for signal 1 (- 500 timer 2 counts ^ 200 counts). at fOSC = 12 MHz) and 0.2 ms for signal 2 (- Thus compare mode 1 must be used, because in this mode both transitions can be preset by software.
^ Timer 2 may run with its full period from 0000, overflowing at a count rate of 65.535 ( - 0FFFF H). External interrupts INT4 and INT5 are enabled as compare interrupts and the compare registers CC1 and CC2 are initialized to 50 % duty cycle thus containing a value of 250 and 100, respectively. The contents of the port latches must be preprogrammed to a complementary level which will appear after the corresponding compare event.
Now timer 2 is started. The first compare interrupt occurs after 100 timer increments caused by the contents of register CC2. Figure 10-1 illustrates the task schedule of the program. Every compare event causes an interrupt request, which is served after a certain response time (depending on the current task being in progress). There are a few jobs to be done, which are described in the following.
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Application Examples
Figure 10-1 Task Schedule for "Additive Compare" Program The interrupt routine has to calculate the next compare value for the current channel (e.g. CC2): TCCnext = TCCact + (TCCtot - TCCduty) where TCCnext TCCtot is the next compare value in CC2 is the (constant) total number of counts for one PWM cycle ( = 200 for PWM channel 2) is the actual compare register contents which just caused the interrupt is the (variable) count determining the duty cycle of the PWM signal.
TCCact TCCduty
The interrupt routine may be left when - TCCnext is loaded to register CC2 - the port latch is complemented and prepared for the next transition and - a user-defined flag is set to mark that this PWM cycle is now completed.
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Application Examples
The same calculation must be performed when register CC1 has had its match and has caused an interrupt for PWM channel 1. But this is done independently from channel 2 since both channels have their own interrupt request flags. When either of the two count values of TCCnext has been reached by timer 2 (in our example, channel 1 is first) then the corresponding interrupt routine polls the user flag and is informed that a new PWM cycle is to be generated. It therefore calculates the next compare value to: TCCnext = TCCact + TCCduty where TCCduty may be a new value for the duty cycle calculated in another task of the program. 10.1.2 Sine-Wave Generation with a CMx Registers/Compare Timer Configuration The following example of a PWM generation demonstrates the use of some important features of the SAB 80C517s CCU: - flexibly programmable compare timer with 16-bit reload and 8 selectable input clocks (fOSC/2 to fOSC/256) - "TOC-loading" mechanism to reduce interrupt load of the CPU The above features allow: - PWM generation for digital-to-analog conversion with extremely low external hardware costs (simple passive RC filter or any other integrating device) - output frequencies from less than 1 Hz (16-bit reload, timer input clock of fOSC/256) to 3 MHz (2-bit reload, timer input clock of fOSC/2) The following paragraphs do not contain a basic description of PWM generation with microcontrollers but rather should give an idea of how to use the CCU of the SAB 80C517 in this kind of applications. Please refer to other literature for a general description of the pulse width modulation. The example in the following uses typical parameters: a PWM frequency above the audible range (23.4 kHz), with 8-bit resolution. The PWM may, for instance, be used to generate a sine-wave via a low-cost RC filter. To simplify matters, just one PWM channel is used in this example. The SAB 80C517, however, can drive up to eight channels with the fast compare timer.
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Application Examples
Explanation of a Few Terms - Pulse width modulation In our case the PWM is used to synthesize a sine-wave. This means that a digital output signal is periodically varied in the length of its high or low time (= duty cycle). One high and one low time together make up a sample point of the sine-wave to be synthesized. The generation of the sinewave out of the modulated digital signal is done by a low-pass filter. - PWM frequency In this example the switching frequency of the PWM signal is fixed. The frequency is determined by the reload value ( resolution) and the input clock of the timer. - 8-bit resolution This means that only eight bits of the 16-bit wide timer and compare circuitry are used to generate the PWM signal ( faster PWM frequency). Thus the duty cycle of the signal is programmable in 256 steps. Each step represents a quantum of one machine state or 166.6 ns at fOSC = 12 MHz (256 x 166.6 ns = 42.649 s; 1/42.649 s = 23.4 kHz) Configuration of the CCU To generate a sine-wave, the duty cycle of a PWM signal must be varied periodically, as mentioned above. One PWM period (or one sample point) is represented by a full compare timer period. The high-to-low transition of the PWM signal takes place upon every compare timer overflow, the lowto-high transition is programmable and takes place when the timer count matches the contents of the compare register ( compare mode 0). In the worst case (maximum sine-wave frequency), the contents of the compare register must be reloaded in every compare timer period. - Compare timer setup Input clock The input clock is set to fOSC/2. This can be done in special function register CTCON. In this case the timer is incremented every machine cycle (166.6 ns at 12 MHz). Reload The reload register CTRELH (high byte) is set to 0FFH, CTRELL (low byte) must contain 00H. Thus the timer counts from 0FF00H to 0FFFFH (= 8-bit reload 256 steps).
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Application Examples
Figure 10-2 PWM Generation for Sine-Wave Synthesis
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Application Examples
- Compare Setup Compare mode Compare register CM0 (consisting of CMH0 and CML0) is used in compare mode 0. This means bit CMSEL.0 must be set (in register CMSEL) to assign CM0 to the compare timer and switch on compare mode 0. Enable port output The compare is enabled with SFR bit CMEN.0 in register CMEN. The corresponding compare output pin is port 4.0. - Interrupts Since the compare value may be varied in every compare timer period, it is most effective to use the compare timer overflow interrupt for reloading the compare register CM0 with a new value. Enable Interrupt The compare timer overflow interrupt is enabled by SFR bit ECT in register IEN2. The general enable flag EAL in register IEN0 must be set, too. The Program Variation of the duty cycle of the PWM signal is done by a variation of the contents of the compare register CM0. CM0 is loaded with new compare values in an (high prioritized) interrupt routine. This makes the loading independent from other tasks running on the CPU. The new compare values are loaded by a cyclic look-up table routine. The table is located in the ROM and contains the compare values for every sample point. (In our case the sine-wave is synthesized by six sample points.) The program flow is best described by a program flow chart (see figure 10-3). The following paragraphs give some additional details. - Main Program CCU and interrupt initialization is done according to the previous description of the CCU configuration. There is no other task in this application to be done in the main program. The controller is free for any other job (e.g. I/O, control algorithms, adapting the sine wave table, etc.). - Interrupt Service Routine The interrupt program contains the table look-up routine only. This routine is illustrated in figure 10-3 and performs the following two little jobs: - managing the table pointer - loading the CM0-register.
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Application Examples
Figure 10-3 Program Flow Charts The interrupt routine takes full advantage of the TOC loading. The interrupt routine is always vectored to some time after a compare timer overflow. This means that the new compare value is moved to CM0 at an undefined moment in the current timer period. The moment depends on the interrupt response time (uncertainty of 3 to 9 machine cycles) and on the length of the interrupt routine itself (perhaps there are more channels to serve), etc. Without any further provisions (like the TOC loading) there would be no chance for loading an early compare value (e.g. CM0 = 0000H) because the timer would have passed these early counts before the loading was completed. The TOC loading now solves the above problem. The interrupt service routine is always "thinking" one cycle in advance. It actually loads the compare value (or sample point) for the next timer period. Thus, the CPU has one full timer period to serve all compares. The compare value loaded to the CM0 register by the interrupt routine will be immediately transferred to the actual compare latch at the next compare timer overflow. This overflow then again requests a new interrupt service routine.
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Application Examples
Conclusion This application example is meant to show that the CCU of the SAB 80C517 is able to generate very fast PWM signals with low CPU effort. Small single-chip systems which have to manage PWM periods below 50 microseconds require a very efficient on-chip timer hardware to leave enough CPU time to perform other control tasks in real time. The SAB 80C517 takes advantage of the fast compare timer and the TOC loading mechanism to meet the above requirements. 10.2 Using an SAB 80C537 with External Program Memory and Additional External Data Memory
Figure 10-4 shows an example of how to connect an external program and data memory to the SAB 80C517/80C537. For the program memory a standard EPROM 2764A is used. An 8-Kbyte static RAM 5565 serves as external data memory. The 74HCT573 works as address latch. The address space ranges from 0 to 1FFFH (8 Kbyte). Pin EA is tied low, so all program memory accesses are done from external memory. Port 0 is the multiplexed address/data bus, while port 2 always emits the high order byte of the address. Therefore, in this configuration port 0 and port 2 must not be used as general-purpose l/O ports.
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Application Examples
Figure 10-4 Connecting the SAB 80C517 with External Program and Data Memory
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High-Performance 8-Bit CMOS Single-Chip Microcontroller
Advanced Information SAB 80C517 SAB 80C537
q q q q
SAB 80C517/80C537
Microcontroller with factory mask-programmable ROM Microcontroller for external ROM
q
q q
q
Versions for 12 MHz and 16 MHz operating frequency 8 K x 8 ROM (SAB 80C517 only) 256 x 8 on-chip RAM Superset of SAB 80C51 architecture: 1 s instruction cycle time at 12 MHz 750 ns instruction cycle time at 16 MHz 256 directly addressable bits Boolean processor 64 Kbyte external data and program memory addressing Four 16-bit timer/counters Powerful 16-bit compare/capture unit (CCU) with up to 21 high-speed or PWM output channels and 5 capture inputs Versatile "fail-safe" provisions
q q q q q q q q
q
Fast 32-bit division, 16-bit 2 multiplication, 32-bit normalize and shift by peripheral MUL/DIV unit (MDU) Eight data pointers for external memory addressing Fourteen interrupt vectors, four priority levels selectable 8-bit A/D converter with 12 multiplexed inputs and programmable ref. voltages Two full duplex serial interfaces Fully upward compatible with SAB 80C515 Extended power saving modes Nine ports: 56 I/O lines, 12 input lines Two temperature ranges available: 0 to 70 oC - 40 to 85 oC Plastic packages: P-LCC-84, P-MQFP-100-2
SAB 80C517/80C537
Semiconductor Group
265
04.95
SAB 80C517/80C537
The SAB 80C517/80C537 is a high-end member of the Siemens SAB 8051 family of microcontrollers. It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture. ACMOS is a technology which combines high-speed and density characteristics with low-power consumption or dissipation. While maintaining all the SAB 80C515 features and operating characteristics the SAB 80C517 is expanded in its arithmetic capabilities, "fail-safe" characteristics, analog signal processing and timer capabilities. The SAB 80C537 is identical with the SAB 80C517 except that it lacks the on-chip program memory. The SAB 80C517/SAB 80C537 is supplied in a 84 pin plastic leaded chip carrier package (P-LCC-84) and in a 100-pin plastic quad metric flat package (P-MQFP-100-2).
Ordering Information Type SAB 80C517-N SAB 80C517-M SAB 80C537-N SAB 80C537-M SAB 80C517-N-T40/85 SAB 80C517-M-T40/85 SAB 80C537-N-T40/85 SAB 80C537-M-T40/85 SAB 80C517-N16 SAB 80C517-M16 SAB 80C537-N16 SAB 80C537-M16 Ordering Code Package Q67120-C397 TBD Q67120-C452 TBD Q67120-C483 TBD Q67120-C484 TBD Q67120-C723 TBD Q67120-C722 TBD P-LCC-84 Description 8-bit CMOS Microcontroller
with factory mask-programmaP-MQFP-100-2 ble ROM, 12 MHz for external memory, 12 MHz
P-LCC-84 P-MQFP-100-2 P-LCC-84
with factory mask-programmable ROM, 12 MHz, P-MQFP-100-2 ext. temperature - 40 to 85 C
P-LCC-84
for external ROM, 12 MHz, P-MQFP-100-2 ext. temperature - 40 to 85 C with mask-programmable ROM,16 MHz ext. temperature P-MQFP-100-2 - 40 to 110 C for external memory, 16 MHz with mask-programmable ROM, 16 MHz ext. temperature - 40 to 85 C with factory mask-programmable ROM, 12 MHz
P-LCC-84
P-LCC-84 P-MQFP-100-2 P-LCC-84
SAB 80C517-N16-T40/85 Q67120-C724
SAB 80C517-16-N-T40/85 Q67120-C725
P-LCC-84
Semiconductor Group
266
SAB 80C517/80C537
Logic Symbol
Semiconductor Group
267
SAB 80C517/80C537
Pin Configuration (P-LCC-84)
Semiconductor Group
268
SAB 80C517/80C537
Pin Configuration (P-MQFP-100-2) Semiconductor Group 269
SAB 80C517/80C537
Pin Definitions and Functions Symbol Pin Number P-LCC-84 P4.0 - P4.7 1- 3, 5 - 9 P-MQFP-100-2 64 - 66, 68 - 72 I/O Port 4 is a bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. This port also serves alternate compare functions. The secondary functions are assigned to the pins of port 4 as follows: - CM0 (P4.0): Compare Channel 0 - CM1 (P4.1): Compare Channel 1 - CM2 (P4.2): Compare Channel 2 - CM3 (P4.3): Compare Channel 3 - CM4 (P4.4): Compare Channel 4 - CM5 (P4.5): Compare Channel 5 - CM6 (P4.6): Compare Channel 6 - CM7 (P4.7): Compare Channel 7 Power saving modes enable/ Start Watchdog Timer A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. I/O *) Function
PE/SWD
4
67
I
*
I = Input O = Output
Semiconductor Group
270
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 RESET 10 P-MQFP-100-2 73 I RESET A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C517. A small internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. Reference voltage for the A/D converter. Reference ground for the A/D converter. I Port 7 is an 8-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the lower 8-bit of the multiplexed analog inputs of the A/D converter, simultaneously. I/O *) Function
VAREF VAGND
P7.7 -P7.0
11 12 13 - 20
78 79 80 - 87
*
I = Input O = Output
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271
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 P3.0 - P3.7 21 - 28 P-MQFP-100-2 90 - 97 I/O Port 3 is a bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 3 also contains the interrupt, timer, serial port 0 and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: - R x D0 (P3.0): receiver data input (asynchronous) or data input/output (synchronous) of serial interface - T x D0 (P3.1): transmitter data output (asynchronous) or clock output (synchronous) of serial interface 0 - INT0 (P3.2): interrupt 0 input/timer 0 gate control - INT1 (P3.3): interrupt 1 input/timer 1 gate control - T0 (P3.4): counter 0 input - T1 (P3.5): counter 1 input - WR (P3.6): the write control signal latches the data byte from port 0 into the external data memory - RD (P3.7): the read control signal enables the external data memory to port 0
*
I/O *) Function
I = Input O = Output
Semiconductor Group
272
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 P1.7 - P1.0 29 - 36 P-MQFP-100-2 98 - 100, 1, 6 - 9 I/O Port 1 is a bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. It is used for the low order address byte during program verifi-cation. It also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: - INT3/CC0 (P1.0): interrupt 3 input/ compare 0 output / capture 0 input - INT4/CC1 (P1.1): interrupt 4 input / compare 1 output /capture 1 input - INT5/CC2 (P1.2): interrupt 5 input / compare 2 output /capture 2 input - INT6/CC3 (P1.3): interrupt 6 input / compare 3 output /capture 3 input - INT2/CC4 (P1.4): interrupt 2 input / compare 4 output /capture 4 input - T2EX (P1.5): timer 2 external reload trigger input - CLKOUT (P1.6): system clock output - T2 (P1.7): counter 2 input
*
I/O *) Function
I = Input O = Output
Semiconductor Group
273
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 XTAL2 39 P-MQFP-100-2 12 - XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL1 Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is devided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Port 2 is a bidirectional I/O port with internal pull-up resistors. Port 2 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as in-puts. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-up resistors when issuing 1 s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. I/O *) Function
XTAL1
40
13
-
P2.0 - P2.7
41 - 48
14 - 21
I/O
*
I = Input O = Output
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274
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 PSEN 49 P-MQFP-100-2 22 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal pro-gram execution. The Address Latch Enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than 8192. When held at low level, the SAB 80C517 fetches all instructions from external program memory. For the SAB 80C537 this pin must be tied low Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1 s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-up resistors when issuing 1 s. Port 0 also outputs the code bytes during program verification in the SAB 83C517. External pull-up resistors are required during program verification. I/O *) Function
ALE
50
23
O
EA
51
24
I
P0.0 - P0.7
52 - 59
26 - 27, 30 - 35
I/O
*
I = Input O = Output
Semiconductor Group
275
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 P5.7 - P5.0 61 - 68 P-MQFP-100-2 37 - 44 I/O Port 5 is a bidirectional I/O port with internal pull-up resistors. Port 5 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. This port also serves the alternate function "Concurrent Compare". The secondary functions are assigned to the port 5 pins as follows: - CCM0 (P5.0): concurrent compare 0 - CCM1 (P5.1): concurrent compare 1 - CCM2 (P5.2): concurrent compare 2 - CCM3 (P5.3): concurrent compare 3 - CCM4(P5.4): concurrent compare 4 - CCM5 (P5.5): concurrent compare 5 - CCM6 (P5.6): concurrent compare 6 - CCM7(P5.7): concurrent compare 7 Oscillator Watchdog Enable A high level on this pin enables the oscillator watchdog. When left unconnected this pin is pulled high by a weak internal pull-up resistor. When held at low level the oscillator watchdog function is off. I/O *) Function
OWE
69
45
I
*
I = Input O = Output
Semiconductor Group
276
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 P6.0 - P6.7 70 - 77 P-MQFP-100-2 46 - 50, 54 - 56 I/O Port 6 is a bidirectional I/O port with internal pull-up resistors. Port 6 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 6 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 6 also contains the external A/D converter control pin and the transmit and receive pins for serial channel 1. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 6, as follows: - ADST (P6.0): external A/D converter start pin - R x D1 (P6.1): receiver data input of serial interface 1 - T x D1 (P6.2): transmitter data output of serial interface 1 P8.0 - P8.3 78 - 81 57 - 60 I Port 8 is a 4-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the higher 4-bit of the multiplexed analog inputs of the A/D converter, simultaneously I/O *) Function
*
I = Input O = Output
Semiconductor Group
277
SAB 80C517/80C537
Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC-84 RO 82 P-MQFP-100-2 61 O Reset Output This pin outputs the internally synchronized reset request signal. This signal may be generated by an external hardware reset, a watchdog timer reset or an oscillator watch-dog reset. The reset output is active low. Circuit ground potential Supply Terminal for all operating modes Not connected I/O *) Function
VSS VCC N.C.
37,60, 83 38,84 -
10, 62 11, 63 2 - 5, 25, 28 - 29, 36, 51 - 53, 74 - 77; 88 - 89
- - -
*
I = Input O = Output
Semiconductor Group
278
SAB 80C517/80C537
Figure 1 Block Diagram Semiconductor Group 279
SAB 80C517/80C537
Functional Description The SAB 80C517 is based on 8051 architecture. It is a fully compatible member of the Siemens SAB 8051/80C51 microcontroller family being a significantly enhanced SAB 80C515. The SAB 80C517 is therefore 100 % compatible with code written for the SAB 80C515. CPU Having an 8-bit CPU with extensive facilities for bit-handling and binary BCD arithmetics the SAB 80C517 is optimized for control applications. With a 12 MHz crystal, 58% of the instructions execute in 1 s. Being designed to close the performance gap to the 16-bit microcontroller world, the SAB 80C517's CPU is supported by a powerful 32-/16-bit arithmetic unit and a more flexible addressing of external memory by eight 16-bit datapointers. Memory Organisation According to the SAB 8051 architecture, the SAB 80C517 has separate address spaces for program and data memory. Figure 2 illustrates the mapping of address spaces.
Figure 2 Memory Mapping Semiconductor Group 280
SAB 80C517/80C537
Program Memory The SAB 80C517 has 8 KByte of on-chip ROM, while the SAB 80C537 has no internal ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls whether program fetches below address 2000H are done from internal or external memory. Data Memory The data memory space consists of an internal and an external memory space. External Data Memory Up to 64 KByte external data memory can be addressed by instructions that use 8-bit or 16-bit indirect addressing. For 8-bit addressing MOVX instructions utilizing registers R0 and R1 can be used. A 16-bit external memory addressing is supported by eight 16-bit datapointers. Multiple Datapointers As a functional enhancement to standard 8051 controllers, the SAB 80C517 contains eight 16-bit datapointers. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointers is done in special function register DPSEL (data pointer select, addr. 92H). Figure 3 illustrates the addressing mechanism. Internal Data Memory The internal data memory is divided into three physically distinct blocks: - the lower 128 bytes of RAM including four banks of eight registers each - the upper 128 byte of RAM - the 128 byte special function register area. A mapping of the internal data memory is also shown in figure 2. The overlapping address spaces are accessed by different addressing modes. The stack can be located anywhere in the internal data memory.
Semiconductor Group
281
SAB 80C517/80C537
Figure 3 Addressing of External Data Memory
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282
SAB 80C517/80C537
Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 81 special function registers include arithmetic registers, pointers, and registers that provide an interface between the CPU and the on-chip peripherals. There are also 128 directly addressable bits within the SFR area. The special function registers are listed in table 1. In this table they are organized in groups which refer to the functional blocks of the SAB 80C517. Block names and symbols are listed in alphabetical order. Table 1 Special Function Register Address CPU Register ACC B DPH DPL DPSEL PSW SP ADCON0 ADCON1 ADDAT DAPR IEN0 CTCON 2) IEN1 IEN2 IP0 IP1 IRCON TCON 2) T2CON 2) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register D/AConverter Program Register Register 0E0H 1) 0F0H 1) 83H 82H 92H 0D0H 1) 81H 0D8H 1) 0DCH 0D9H 0DAH Contents after Reset 00H 00H 00H 00H XXXX.X000B 3) 00H 07H 00H XXXX.0000B 3) 00H 00H 00H 0XXX.0000B 00H XXXX.00X0B 3) 00H XX00 0000B 00H 00H 00H
A/DConverter
Interrupt System
Interrupt Enable Register 0 0A8H 1) Com. Timer Control Register 0E1H Interrupt Enable Register 1 0B8H 1) Interrupt Enable Register 2 9AH Interrupt Priority Register 0 0A9H Interrupt Priority Register 1 0B9H Interrupt Request Control Register 0C0H 1) Timer Control Register 88H 1) Timer 2 Control Register 0C8H
1) 2) 3)
Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. X means that the value is indeterminate and the location is reserved
Semiconductor Group
283
SAB 80C517/80C537
Table 1 Special Function Register (cont'd) Address MUL/DIV Unit Register ARCON MD0 MD1 MD2 MD3 MD4 MD5 Name Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Register 0EFH 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH Contents after Reset 0XXX.XXXXB3) XXH3) XXH3) XXH3) XXH3) XXH3) XXH3)
1) 2) 3)
Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. X means that the value is indeterminate and the location is reserved
Semiconductor Group
284
SAB 80C517/80C537
Table 1 Special Function Register (cont'd) Address Compare/ CaptureUnit (CCU) Register CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL CTCON CTRELH CTRELL TH2 TL2 T2CON Name Comp./Capture Enable Reg. Comp./Capture Enable 4 Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 4, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Comp./Capture Reg. 4, Low Byte Compare Enable Register Compare Register 0, High Byte Compare Register 1, High Byte Compare Register 2, High Byte Compare Register 3, High Byte Compare Register 4, High Byte Compare Register 5, High Byte Compare Register 6, High Byte Compare Register 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Com. Timer Control Reg. Com. Timer Rel. Reg., High Byte Com. Timer Rel. Reg., Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Register 0C1H 0C9H 0C3H 0C5H 0C7H 0CFH 0C2H 0C4H 0C6H 0CEH 0F6H 0D3H 0D5H 0D7H 0E3H 0E5H 0E7H 0F3H 0F5H 0D2H 0D4H 0D6H 0E2H 0E4H 0E6H 0F2H 0F4H 0F7H 0CBH 0CAH 0E1H 0DFH 0DEH 0CDH 0CCH 0C8H 1) Contents after Reset 00H X000.0000B3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0XXX.0000B3) 00H 00H 00H 00H 00H
1) 2) 3)
Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. X means that the value is indeterminate and the location is reserved
Semiconductor Group
285
SAB 80C517/80C537
Table 1 Special Function Register (cont'd) Address Ports Register P0 P1 P2 P3 P4 P5 P6 P7 P8 PCON ADCON0 2) PCON 2) S0BUF S0CON S0RELL 4) S0RELH S1BUF S1CON S1REL S1RELH 4) Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD IEN0 2) IEN1 2) IP0 2) IP1 2) WDTREL
4)
Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6, Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4-bit Power Control Register A/D Converter Control Reg. Power Control Register Serial Channel 0 Buffer Reg. Serial Channel 0 Control Reg. Serial Channel 0, Reload Reg., low byte Serial Channel 0, Reload Reg., high byte Serial Channel 1 Buffer Reg., Serial Channel 1 Control Reg. Serial Channel 1 Reload Reg., low byte Serial Channel 1, Reload Reg., high byte Timer Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Watchdog Timer Reload Reg.
Register 80H 1) 90H 1) 0A0H 1) 0B0H 1) 0E8H 1) 0F8H 1) 0FAH 0DBH 0DDH 87H 0D8H 1) 87H 99H 98H 1) 0AAH 0BAH 9CH 9BH 9DH 0BBH 88H 1) 8CH 8DH 8AH 8BH 89H 0A8H 1) 0B8H 1) 0A9H 0B9H 86H
Contents after Reset FFH FFH FFH FFH FFH FFH FFH XXH 3) XXH 3) 00H 00H 00H XXH 3) 00H 0D9H XXXX.XX11B3) 0XXH 3) 0X00.000B 3) 00H XXXX.XX11B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H XX00.0000B 3) 00H
Pow.Sav. Modes Serial Channels
Watchdog
1) 2) 3) 4)
Bit-addressable special function registers. This special function register is listed repeatedly since some bits of it also belong to other functional blocks. X means that the value is indeterminate and the location is reserved. These registers are available in the CA step and later steps.
Semiconductor Group
286
SAB 80C517/80C537
A/D Converter The SAB 80C517 contains an 8-bit A/D Converter with 12 multiplexed input channels which uses the successive approximation method. It takes 7 machine cycles to sample an analog signal (during this sample time the input signal should be held constant); the total conversion time (including sample time) is 13 machine cycles (13 s at 12 MHz oscillator frequency). Conversion can be programmed to be single or continuous; at the end of a conversion an interrupt can be generated. A unique feature is the capability of internal reference voltage programming. The internal reference voltages VIntAREF and VIntAGND for the A/D converter are both programmable to one of 16 steps with respect to the external reference voltages. This feature permits a conversion with a smaller internal reference voltage range to gain a higher resolution. In addition, the internal reference voltages can easily be adapted by software to the desired analog input voltage range (see table 2). Table 2 Adjustable Internal Reference Voltages Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DAPR (.3-.0) DAPR (.7-.4) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VIntAGND 0.0 0.3125 0.625 0.9375 1.25 1.5625 1.875 2.1875 2.5 2.8125 3.125 3.4375 3.75 - - - VIntAREF 5.0 - - - 1.25 1.5625 1.875 2.1875 2.5 2.8125 3.125 3.4375 3.75 4.0625 4.375 4.68754
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SAB 80C517/80C537
Figure 4 Block Diagram A/D Converter
Semiconductor Group
288
SAB 80C517/80C537
Compare/Capture Unit (CCU) The compare capture unit is a complex timer/register array for applications that require high speed I/O, pulse width modulation and more timer/counter capabilities. The CCU contains - one 16-bit timer/counter (timer 2) with 2-bit prescaler, reload capability and a max. clock frequency of fOSC /12 (1 MHz with a 12 MHz crystal). - one 16-bit timer (compare timer) with 8-bit prescaler, reload capability and a max. clock frequency of fOSC/2 (6 MHz with a 12 MHz crystal). - thirteen 16-bit compare registers. - five of which can be used as 16-bit capture registers. - up to 21 output lines controlled by the CCU. - seven interrupts which can be generated by CCU-events. Figure 5 shows a block diagram of the CCU. Eight compare registers (CM0 to CM7) can individually be assigned to either timer 2 or the compare timer. Diagrams of the two timers are shown in figures 6 and 7. The four compare/capture registers and the compare/reload/capture register are always connected to timer 2. Dependent on the register type and the assigned timer two compare modes can be selected. Table 3 illustrates possible combinations and the corresponding output lines. Table 3 CCU Configuration Assigned Timer Timer 2 Compare Register CRCH/CRCL CC1H/CC1L CC2H/CC2L CC3H/CC3L CC4H/CC4L CC4H/CC4L : CC4H/CC4L CM0H/CM0L : CM7H/CM7L Compare timer CM0H/CM0L : : CM7H/CM7L Compare Output at Possible Modes P1.0/INT3/CC0 P1.0/INT4/CC1 P1.0/INT5/CC2 P1.0/INT6/CC3 P1.0/INT2/CC4 P5.0/CCM0 : P5.7/CCM7 P4.0/CM0 : P4.7/CM7 P4.0/CM0 : : P4.7/CM7 Comp. mode 0, 1 + Reload Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 1 : Comp. mode 1 Comp. mode 1 : Comp. mode 1 Comp. mode 0 (with add. latches) : : Comp. mode 0 (with shadow latches)
Semiconductor Group
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SAB 80C517/80C537
Figure 5 Block Diagram of the Compare/Capture Unit
Semiconductor Group
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Compare In the compare mode, the 16-bit values stored in the dedicated compare registers are compared to the contents of the timer 2 register or the compare timer register. If the count value in the timer registers matches one of the stored values, an appropriate output signal is generated and an interrupt is requested. Two compare modes are provided: Mode 0: Mode 1: Upon a match the output signal changes from low to high. It goes back to low level when the timer overflows. The transition of the output signal can be determined by software. A timer overflow signal doesn't affect the compare-output.
Compare registers CM0 to CM7 use additional compare latches when operated in mode 0. Figure 8 shows the function of these latches. The latches are implemented to prevent from loss of compare matches which may occur when loading of the compare values is not correlated with the timer count. The compare latches are automatically loaded from the compare registers at every timer overflow. Capture This feature permits saving of the actual timer/counter contents into a selected register upon an external event or a software write operation. Two modes are provided to latch the current 16-bit value of timer 2 registers into a dedicated capture register. Mode 0: Mode 1: Capture is performed in response to a transition at the corresponding port pins CC0 to CC3. Write operation into the low-order byte of the dedicated capture register causes the timer 2 contents to be latched into this register.
Reload of Timer 2 A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the 8-bit registers CRCL and CRCH. There are two modes from which to select: Mode 0: Mode 1: Reload is caused by a timer overflow (auto-reload). Reload is caused in response to a negative transition at pin T2EX (P1.5), which also can request an interrupt.
Timer/Counters 0 and 1 These timer/counters are fully compatible with timer/counter 0 or 1 of the SAB 8051 and can operate in four modes: Mode 0: Mode 1: Mode 2: Mode 3: 8-bit timer/counter with 32:1 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit auto reload Timer/counter 0 is configured as one 8-bit timer; timer/counter 1 in this mode holds its count.
External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Semiconductor Group 291
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Figure 6 Block Diagram of Timer 2
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Figure 7 Block Diagram of the Compare Timer
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Figure 8 Compare-Mode 0 with Registers CM0 to CM7
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Interrupt Structure The SAB 80C517 has 14 interrupt vectors with the following vector addresses and request flags. Table 4 Interrupt Sources and Vectors Source (Request Flags) IE0 TF0 IE1 TF1 RI0/TI0 TF2 + EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 RI1/TI1 CTF Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 0083H 009BH Vector External interrupt 0 Timer 0 overflow External interrupt 1 Timer 1 overflow Serial channel 0 Timer 2 overflow/ext. reload A/D converter External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Serial channel 1 Compare timer overflow
Each interrupt vector can be individually enabled/disabled. The response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles. External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable) at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition. The external interrupts 2 to 6 are combined with the corresponding alternate functions compare (output) and capture (input) on port 1. For programming of the priority levels the interrupt vectors are combined to pairs or triples. Each pair or triple can be programmed individually to one of four priority levels by setting or clearing one bit in special function register IP0 and one in IP1. Figure 9 shows the interrupt request sources, the enabling and the priority level structure.
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Figure 9 Interrupt Structure Semiconductor Group 296
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Figure 9 (cont'd) Interrupt Structure Semiconductor Group 297
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Multiplication/Division Unit This on-chip arithmetic unit provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are integer operations. Operation 32-bit/16-bit 16-bit/16-bit 16-bit 16-bit 32-bit normalize 32-bit shift left/right
1) 2)
Result 32-bit 16-bit 32-bit - -
Remainder 16-bit 16-bit - - -
Execution Time 6 t cy 1) 4 t cy 4 t cy 6 t cy 2) 6 t cy 2)
1 tcy = 1 s @ 12 MHz oscillator frequency. The maximal shift speed is 6 shifts/cycle.
The MDU consists of six registers used for operands and results and one control register. Operation of the MDU can be divided in three phases:
Figure 10 Operation of the MDU
To start an operation, register MD0 to MD5 (or ARCON) must be written to in a certain sequence according to table 5 or 6. The order the registers are accessed determines the type of the operation. A shift operation is started by a final write operation to register ARCON (see also the register description). Semiconductor Group 298
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Table 5 Programming the MDU for Multiplication and Division Operation First Write 32-Bit/16-Bit MD0 MD1 MD2 MD3 MD4 MD5 MD0 MD1 MD2 MD3 MD4 MD5 D'endL D'end D'end D'endH D'orL D'orH QuoL Quo Quo QuoH RemL RemH 16-Bit/16-Bit MD0 MD1 MD4 MD5 MD0 MD1 MD4 MD5 D'endL D'end D'end D'endH D'orL D'orH QuoL QuoH RemL RemH 16-Bit * 16-Bit MD0 MD4 MD1 MD5 MD0 MD1 MD2 MD3 PrH M'andL M'orL M'andH M'orH PrL
Last Write First Read
Last Read
Table 6 Shift Operation with the CCU Operation First Write Normalize, Shift Left, Shift Right MD0 MD1 MD2 MD3 ARCON MD0 MD1 MD2 MD3 least significant byte
Last Write First Read
most significant byte start of conversion least significant byte
Last Read Abbreviations D'end D'or M'and M'or Pr Rem Quo ...L ...H : : : : : : : : :
most significant byte
Dividend, 1st operand of division Divisor, 2nd operand of division Multiplicand, 1st operand of multiplication Multiplicator, 2nd operand of multiplication Product, result of multiplication Remainder Quotient, result of division means, that this byte is the least significant of the 16-bit or 32-bit operand means, that this byte is the most significant of the 16-bit or 32-bit operand
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I/O Ports The SAB 80C517 has seven 8-bit I/O ports and two input ports (8-bit and 4-bit wide). Port 0 is an open-drain bidirectional I/O port, while ports 1 to 6 are quasi-bidirectional I/O ports with internal pull-up resistors. That means, when configured as inputs, ports 1 to 6 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. Port 0 and port 2 can be used to expand the program and data memory externally. During an access to external memory, port 0 emits the low-order address byte and reads/writes the data byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Port 1, 3, 4, 5 and port 6 provide several alternate functions. Please see the "Pin Description" for details. Port pins show the information written to the port latches, when used as general purpose port. When an alternate function is used, the port pin is controlled by the respective peripheral unit. Therefore the port latch must contain a "one" for that function to operate. The same applies when the port pins are used as inputs. Ports 1, 3, 4 and 5 are bit- addressable. The SAB 80C517 has two dual-purpose input ports. The twelve port lines at port 7 and port 8 can be used as analog inputs for the A/D converter. If input voltages at P7 and P8 meet the specified digital input levels (VIL and VIH) the port can also be used as digital input port.
Semiconductor Group
300
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Power Saving Modes The SAB 80C517 provides - due to Siemens ACMOS technology - three modes in which power consumption can be significantly reduced. - The Slow Down Mode The controller keeps up the full operating functionality, but is driven with the eighth part of its normal operating frequency. Slowing down the frequency greatly reduces power consumption. - The Idle Mode The CPU is gated off from the oscillator, but all peripherals are still supplied by the clock and able to work. - The Power Down Mode Operation of the SAB 80C517 is stopped, the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. All of these modes are entered by software. Special function register PCON (power control register, address is 87H) is used to select one of these modes. Hardware Enable for Power Saving Modes A dedicated Pin (PE/SWD) of the SAB 80C517 allows to block the power saving modes. Since this pin is mostly used in noise-critical application it is combined with an automatic start of the Watchdog Timer (see there for further description). PE/SWD = VIH (logic high level): Using of the power saving modes is not possible. The instruction sequences used for entering of these modes will not affect the normal operation of the device. All power saving modes can be activated by software. When left unconnected, Pin PE/SWD is pulled to high level by a weak internal pullup. This is done to provide system protection on default.
PE/SWD = VIL (logic low level):
The logic-level applied to pin PE/SWD can be changed during program execution to allow or to block the use of the power saving modes without any effect on the on-chip watchdog circuitry. Power Down Mode The power down mode is entered by two consecutive instructions directly following each other. The first instruction has to set the flag PDE (power down enable) and must not set PDS (power down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will automatically be cleared after having been set. The instruction that sets bit PDS is the last instruction executed before going into power down mode. The only exit from power down mode is a hardware reset. The status of all output lines of the controller can be looked up in table 7.
Semiconductor Group
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Table 7 Status of External Pins During Idle and Power Down Outputs Last instruction executed from internal code memory Idle ALE PSEN Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 High High Data Data/alternate outputs Data Data/alternate outputs Data/alternate outputs Data/alternate outputs Data/alternate outputs Power down Low Low Data Data/last output Data Data/last output Data/last output Data/last output Data/last output Last instruction executed from external code memory Idle High High Float Data/alternate outputs Address Data/alternate outputs Data/alternate outputs Data/alternate outputs Data/alternate outputs Power Down Low Low Float Data/last output Data Data/last output Data/last output Data/last output Data/last output
Idle Mode During idle mode all peripherals of the SAB 80C517 are still supplied by the oscillator clock. Thus the user has to take care which peripheral should continue to run and which has to be stopped during Idle. The procedure to enter the Idle mode is similar to entering the power down mode. The two bits IDLE and IDLS must be set by to consecutive instructions to minimize the chance of unintentional activating of the idle mode. There are two ways to terminate the idle mode: - The idle mode can be terminated by activating any enabled interrupt. This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLS. - The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still running, the hardware reset must be held active only for two machine cycles for a complete reset. Normally the port pins hold the logical state they had at the time idle mode was activated. If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on. The control signals ALE and PSEN hold at logic high levels (see table 7). Semiconductor Group 302
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Table 8 Baud Rate Generation Function Mode 8-Bit synchronous channel Baud rate *) Serial Interface 0 Mode 0 1 MHz @ f OSC = 12 MHz Serial Interface 1
- -
Baud rate derived from Mode 8-Bit UART Baud rate *)
f OSC
-
Mode 1 1 - 62.5 K 4800, 9600
Mode B 1.5 - 375 K
Baud rate derived from Mode 9-Bit UART
Timer 1
BD
8-bit baud rate generator
Mode 2
Mode 3 1 - 62.5 K Timer 1
Mode A 1.5 - 375 K 8-bit baud rate generator
Baud rate *) 187.5 K/ 375 K Baud rate derived from
fOSC/2
*) Baud rate values are given for 12 MHz oscillator frequency.
Semiconductor Group
303
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Serial Interface 0 Serial Interface 0 can operate in 4 modes: Mode 0: Shift register mode: Serial data enters and exits through RXD0. TXD0 outputs the shift clock 8 data bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. 8-bit UART, variable baud rate: 10-bit are transmitted (through RXD0) or received (through RXD0): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB80 in special function register S0CON. The baud rate is variable. 9-bit UART, fixed baud rate: 11-bit are transmitted (through TXD0) or received (through RXD0): a start bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1). On transmission, the 9th data bit (TB80 in S0CON) can be assigned to the value of 0 or 1. For example, the parity bit (P in the PSW) could be moved into TB80 or a second stop bit by setting TB80 to 1. On reception the 9th data bit goes into RB80 in special function register S0CON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. 9-bit UART, variable baud rate: 11-bit are transmitted (through TXD0) or received (through RXD0): a start bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable.
Mode 1:
Mode 2:
Mode 3:
Variable Baud Rates for Serial Interface 0 Variable baud rates for modes 1 and 3 of serial interface 0 can be derived from either timer 1 or from the oscillator via a special prescaler ("BD"). Timer 1 may be operated in mode 1 (to generate slow baud rates) or mode 2. The dedicated baud rate generator "BD" provides the two standard baud rates 4800 or 9600 baud with 0.16% deviation. Table 8 shows possible configurations and the according baud rates. SAB 80C517 devices with stepping code "CA" or later provide a dedicated baud rate generator for the serial interface 0. This baud rate genertaor is a free running 10-bit timer with programmable reload registers. 2 x f OSC Mode 1.3 baud rate = ----------------------------------------------------10 64 x ( 2 - S0REL ) The default value after reset in the reload registers S0RELL and S0RELH prvide a baud rate of 4.8 kBaud (SMOD = 0) or 9.6 kBaud (SMOD = 1) at 12 MHz oscillator frequency. This guarantees full compatibility to the SAB 80C517 older steppings.
SMOD
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Serial Interface 1 Serial interface 1 can operate in two asynchronous modes: Mode A: 9-bit UART, variable baud rate. 11 bits are transmitted (through TXD0) or received (through RXD0): a start bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1). On transmission, the 9th data bit (TB81 in S1CON) can be assigned to the value of 0 or 1. For example, the parity bit (P in the PSW) could be moved into TB81 or a second stop bit by setting TB81 to 1. On reception the 9th data bit goes into RB81 in special function register S1CON, while the stop bit is ignored. 8-bit UART, variable baud rate. 10 bits are transmitted (through TXD1) or received (through RXD1): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB81 in special function register S1CON.
Mode B:
Variable Baud Rates for Serial Interface 1 Variable baud rates for modes A and B of serial interface 1 can be derived from a dedicated baud rate generator. baud rate clock The baud rate clock (baud rate = --------------------------------------- ) is generated by a 8-bit free 16 running timer with programmable reload register. SAB 80C517 devices with stepping code "CA" or later provide a 10-bit free running timer for baud rate generation. Mode A, B baud rate = --------------------------------------------------------------------10 32 x ( 2 - Reload Value ) Watchdog Units The SAB 80C517 offers two enhanced fail safe mechanisms, which allow an automatic recovery from hardware failure or software upset: - programmable watchdog timer (WDT), variable from 512 ms up to about 1.1 s time out period @12 MHz. Upward compatible to SAB 80515 watchdog. - oscillator watchdog (OWD), monitors the on-chip oscillator and forces the microcontroller to go into reset state, in case the on-chip oscillator fails. Programmable Watchdog Timer The WDT can be activated by hardware or software. Hardware initialization is done when pin PE/SWD (Pin 4) is held high during RESET. The SAB 80C517 then starts program execution with the WDT running. Pin PE/SWD doesn't allow dynamic switching of the WDT. Software initialization is done by setting bit SWDT. A refresh of the watchdog timer is done by setting bits WDT and SWDT consecutively. A block diagram of the watchdog timer is shown in figure 11. When a watchdog timer reset occurs, the watchdog timer keeps on running, but a status flag WDTS is set. This flag can also be manipulated by software. Semiconductor Group 305
fOSC
SAB 80C517/80C537
Figure 11 Block Diagram of the Programmable Watchdog Timer Oscillator Watchdog The oscillator watchdog monitors the on-chip quartz oscillator. A detected oscillator failure (f OSC < appr. 300 kHz) causes a hardware reset. The reset state is held until the on-chip oscillator is working again. The oscillator watchdog feature is enabled by a high level at pin OWE (pin 69). An oscillator watchdog reset sets status flag OWDS which can be examined and modified by software. Figure 12 shows a block diagram of the oscillator watchdog.
Figure 12 Functional Block Diagram of the Oscillator Watchdog
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Instruction Set Summary The SAB 80C517/80C537 has the same instruction set as the industry standard 8051 microcontroller. A pocket guide is available which contains the complete instruction set in functional and hexadecimal order. Furtheron it provides helpful information about Special Function Registers, Interrupt Vectors and Assembler Directives. Literature Information Title Microcontroller Family SAB 8051 Pocket Guide Ordering No. B158-H6497-X-X-7600
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Absolute Maximum Ratings Ambient temperature under bias SAB 80C517/83C537.................................................................................. 0 to 70 oC SAB 80C517/83C537-T40/85.................................................................................... - 40 to 85 oC Storage temperature TST ............................................................................ - 65 to 150 oC Voltage on VCC pins with respect to ground (VSS) ...................................... - 0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS)......................................... - 0.5 to VCC +0.5 V Input current on any pin during overload condition ..................................... - 10mA to +10mA Absolute sum of all input currents during overload condition ..................... |100mA| Power dissipation ........................................................................................ 2 W
Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) theVoltage on VCC pins with respect to ground (VSS) must not exeed the values definded by the absolute maximum ratings.
DC Characteristics
VCC = 5 V 10 %; VSS = 0 V; T A = 0 to 70 oC for the SAB 80C517/83C537 T A = - 40 to 85 oC for the SAB 80C517-/83C537-T40/85
Parameter Symbol Limit Values min. Input low voltage (except EA) Input low voltage (EA) Input high voltage Input high voltage to XTAL2 Input high voltage to RESET Output low voltage (ports 1, 2, 3, 4, 5, 6)
Notes see page 311.
Unit
Test Condition
max. 0.2 VCC- - 0.1 V - - - - - IOL = 1.6 mA1)
V IL VIL1 VIH V IH1 V IH2 VOL
- 0.5 - 0.5 0.2 VCC + 0.9 0.7 VCC 0.6 VCC -
0.2 VCC - V - 0.3 V C C + 0.5 V VCC + 0.5 V VCC + 0.5 V 0.45 V
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DC Characteristics (cont'd) Parameter Symbol Limit Values min. Output low voltage (ports ALE, PSEN, RO) Output high voltage (ports 1, 2, 3, 4, 5, 6) Output high voltage (port 0 in external bus mode, ALE, PSEN, RO) Logic 0 input current (ports 1, 2, 3, 4, 5, 6) Input low current to RESET for reset Input low current (XTAL2) Input low current (OWE, PE/SWD) VOL1 VOH VOH1 - 2.4 0.9 VCC 2.4 0.9 VCC - 10 - 10 - - - 65 - - max. 0.45 - - - - - 70 -100 - 15 - 20 - 650
Unit Test Condition
V V V V V
A A A A A A
IOL = 3.2mA 1) IOH = - 80 A IOH = - 10 A IOH = - 800 A2) IOH = - 80 A2) VIN = 0.45 V VIN = 0.45 V VIN = 0.45 V VIN = 0.45 V VIN = 2 V 0.45 < VIN < VCC10) fC = 1 MHz TA = 25 oC VCC = 5 V,4) VCC = 5 V,5) VCC = 5 V,5) VCC = 5 V,4) VCC = 5 V,5) VCC = 5 V,5) VCC = 2...5.5 V 3)
I IL IIL2 IIL3 I IL4
Logical 1-to-0 transition current ITL (ports 1, 2, 3, 4, 5, 6) Input leakage current (port 0, EA, ports 7, 8) Pin capacitance Power supply current: Active mode, 12 MHz 6) Idle mode, 12 MHz 6) Slow down mode, 12 MHz 6) Active mode, 16 MHz 6) Idle mode, 16 MHz 6) Slow down mode, 16MHz6) Power down Mode
Notes see page 311.
ILI C IO
1
10
pF
ICC ICC I PD
- - - - - - -
40 15 15 52.3 19 19 50
mA mA mA mA mA mA
A
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A/D Converter Characteristics V CC = 5 V 10 %; V SS = 0 V VAREF = VCC 5%; VAGND = VSS 0.2 V; VIntAREF - VIntAGND 1V T A = 0 to 70 oC for the SAB 80C517/83C537 T A = - 40 to 85 oC for the SAB 80C517/83C537-T40/875 Parameter Symbol min. Analog input voltage Analog input capacitance Load time Sample time (incl. load time) Conversion time (incl. sample time) Total unadjusted error Internal reference error VAREF supply current
Notes see page 311.
Limit values typ.
-
Unit
Test Condition
max. V AREF + 0.2 60 2 t CY 7t CY 13 t CY 2 30 V pF s s s LSB mV mA
9)
V AINPUT CI tL tS tC
TUE
VAGND - 0.2 - - - - - - -
25 - - -
7)
7) 7)
7)
VAREF = VCC V AGND = VSS 11)
8) 8)
VIntREFERR I REF
-
5
Semiconductor Group
310
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Notes for pages 308, 309 and 310: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and ports 1, 3, 4, 5 and 6. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt- trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) Power down IPD is measured with all output pins disconnected; EA = RESET = VCC; Port 0 = Port 7 = Port 8 = VCC; XTAL1 = N.C.; XTAL2 = VSS; VAGND= N.C.; VAREF = VCC; PE/SWD = OWE = VSS. 4) ICC (active mode) is measured with all output pins disconnected; XTAL2 driven with clock signal according to the figure below; XTAL1 = N.C.; EA = OWE = PE/SWD = VCC; Port 0 = Port 7 = Port 8 = VCC; RESET = VSS. ICC would be slightly higher if a crystal oscillator is used. 5) IC C (idle mode,) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with clock signal according to the figure below; XTAL1 = N.C.; RESET = OWE = VCC; Port 0 = Port 7 = Port 8 = VCC; EA = PE/SWD = VSS. ICC (slow down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with clock signal according to the figure below; XTAL = N.C.; Port 7 = Port 8 = VCC; EA = PE/SWD = VSS. 6) I CC (max.) at other frequencies is given by: active mode: I CC max = 3.1 * fOSC + 3.0 idle mode: I CC max = 1.0 * fOSC + 3.0 Where fOSC is the oscillator frequency in MHz. I CC values are given in mA and measured at VCC = 5 V (see also notes 4 and 5). 7) The output impedance of the analog source must be low enough to assure full loading of the sample capacitance (CI) during load time (TL ). After charging of the internal capacitance (CI) in the load time (TL) the analog input must be held constant for the rest of the sample time (TS). 8) The differential impedance RD of the analog reference voltage source must be less than 1 k at reference supply voltage. 9) Exceeding the limit values at one or more input channels will cause additional current which is sinked sourced at these channels. This may also affect the accuracy of other channels which are operated within the specification. 10) Only valid for not selected analog inputs. 11) No missing code.
Semiconductor Group
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Clock of Waveform for ICC Tests in Active, Idle Mode and Slow Down Mode
Semiconductor Group
312
SAB 80C517/80C537
AC Characteristics VCC = 5 V 10 %; VSS = 0 V T A = 0 to 70 oC for the SAB 80C517/83C537 T A = - 40 to 85 oC for the SAB 80C517/83C537-T40/85 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)) Parameter Symbol 12 MHz Clock min Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN *) Address valid after PSEN *) Address to valid instruction in Address float to PSEN
*)
Limit Values Variable Clock 1/t CLCL = 3.5 MHz to 12 MHz min. max.
Unit
max.
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIX*) tPXAV*) tAVIV tAZPL
127 53 48 - 58 215 - 0 - 75 - -
- - - 233 - - 150 - 63 - 302 -
2 tCLCL - 40 tCLCL - 30 tCLCL - 35 - tCLCL - 25 3 tCLCL - 35 - 0 - tCLCL - 8 0 -
- - - 4tCLCL - 100 - - 3tCLCL - 100
ns ns ns ns ns ns ns ns
tCLCL - 20 - 5tCLCL - 115
ns ns ns ns
Interfacing the SAB 80C517 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
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AC Characteristics (cont'd) Parameter Symbol 12 MHz Clock min External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid instr in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD WR or RD high to ALE high Address valid to WR Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tWHLH tAVWL tQVWX tQVWX tWHQX tRLAZ 400 400 132 - 0 - - - 200 43 203 33 433 33 - - - - 252 - 97 517 585 300 123 - - - - 0 6 tCLCL - 100 6 tCLCL - 100 2 tCLCL - 30 - 0 - - - 3 tCLCL - 50 - - - 5 tCLCL - 165 - 2 tCLCL - 70 8 tCLCL - 150 9 tCLCL - 165 3 tCLCL + 50 tCLCL +40 - - - - 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. Limit Values Variable Clock 1/t CLCL = 3.5 MHz to 12 MHz min. max. Unit
tCLCL - 40
4 tCLCL - 130 tCLCL - 50 7 tCLCL - 150 tCLCL - 50 -
Semiconductor Group
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AC Characteristics V CC = 5 V 10 %; V SS = 0 V TA= 0 to 70 oC for the SAB 80C517-16/83C537-16 T A = - 40 to 85 oC for the SAB 80C517-16/83C537-16-T40/85 (CL for port 0, ALE and PSEN outputs = 100pF; CL for all outputs = 80 pF) Parameter Symbol 16 MHz Clock min Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instr. in ALE to PSEN PSEN pulse width PSEN to valid instr. in Input instruction hold after PSEN Input instruction float *) after PSEN Address valid after PSEN *) Address to valid instr. in Address float to PSEN
*)
Limit Values Variable Clock 1/t CLCL = 3.5 MHz to 16 MHz min. max.
Unit
max.
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tAZPL
85 33 28 - 38 153 - 0 - 55 - 0
- - - 150 - - 88 - 43 - 198 -
2 tCLCL - 40 tCLCL - 30 tCLCL - 35 - tCLCL - 25 3 tCLCL - 35 - 0 - tCLCL - 8 0- 0
- - - 4tCLCL- 100 - - 3tCLCL - 100 - tCLCL - 20 - 5tCLCL - 115 -
ns ns ns ns ns ns ns ns ns ns ns ns
Interfacing the SAB 80C517 to devices with float times up to 55 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Semiconductor Group
315
SAB 80C517/80C537
AC Characteristics (cont'd) Parameter Symbol 16 MHz Clock min External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD WR or RD high to ALE high Address valid to WR Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tWHLH tAVWL tQVWX tQVWH tWHQX tRLAZ 275 275 90 - 0 - - - 138 23 120 13 288 13 - - - - 148 - 55 350 398 238 103 - - - - 0 6 tCLCL - 100 6 tCLCL - 100 2 tCLCL - 35 - 0 - - - 3 tCLCL - 50 tCLCL - 40 4 tCLCL - 130 tCLCL - 50 7 tCLCL - 150 tCLCL - 50 - - - - 5 tCLCL - 165 - 2 tCLCL - 70 8 tCLCL - 150 9 tCLCL - 165 3 tCLCL + 50 tCLCL + 40 - - - - 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. Limit Values Variable Clock 1/t CLCL = 3.5 MHz to 16 MHz min. max. Unit
Semiconductor Group
316
SAB 80C517/80C537
Program Memory Read Cycle
Data Memory Read Cycle Semiconductor Group 317
SAB 80C517/80C537
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Data Memory Write Cycle
Semiconductor Group
318
SAB 80C517/80C537
AC Characteristics (cont'd) Parameter Symbol Limit Values Variable Clock Frequ. = 3.5 MHz to 12 MHz min External Clock Drive Oscillator period Oscillator frequency High time Low time Rise time Fall time tCLCL 1/tCLCL tCHCX tCLCX tCLCH t CHCL 83.3 3.5 20 20 - - 285 12 - - 20 20 ns MHz ns ns ns ns max. Unit
AC Characteristics (cont'd) Parameter Symbol Limit Values Variable Clock Frequ. = 1 MHz to 16 MHz min External Clock Drive Oscillator period Oscillator frequency High time Low time Rise time Fall time tCLCL 1/tCLCL tCHCX tCLCX tCLCH t CHCL 62.5 3.5 25 25 - - 285 16 - - 20 20 ns MHz ns ns ns ns max. Unit
Semiconductor Group
319
SAB 80C517/80C537
External Clock Cycle
Semiconductor Group
320
SAB 80C517/80C537
AC Characteristics (cont'd) Parameter Symbol 12 MHz Clock Limit Values Variable Clock 1/t CLCL =3.5 MHz to 12 MHz min. max. Unit
min. System Clock Timing ALE to CLKOUT CLKOUT high time CLKOUT low time CLKOUT low to ALE high tLLSH tSHSL tSLSH tSLLH 543 127 793 43
max.
- - - 123
7tCLCL - 40 2tCLCL - 40 10tCLCL - 40 tCLCL - 40
- - - tCLCL + 40
ns ns ns ns
AC Characteristics (cont'd) Parameter Symbol 16 MHz Clock Limit Values Variable Clock 1/t CLCL = 3.5 MHz to 16 MHz min. max. Unit
min. System Clock Timing ALE to CLKOUT CLKOUT high time CLKOUT low time CLKOUT low to ALE high tLLSH tSHSL tSLSH tSLLH 398 85 585 23
max.
- - - 103
7tCLCL - 40 2tCLCL - 40 10tCLCL - 40 tCLCL - 40
- - - tCLCL + 40
ns ns ns ns
Semiconductor Group
321
SAB 80C517/80C537
System Clock Timing
Semiconductor Group
322
SAB 80C517/80C537
ROM Verification Characteristics T A = 25C 5C; V CC = 5 V 10%; V SS = 0 V Parameter Symbol min Limit values max. Unit
ROM Verification Address to valid data ENABLE to valid data tAVQV t ELQV - - 0 4 48 tCLCL 48 tCLCL 48 tCLCL 6 ns ns ns MHz
Data float after ENABLE tEHQZ Oscillator frequency 1/tCLCL
ROM Verification
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA.
Semiconductor Group
323
SAB 80C517/80C537
Recommended Oscillator Circuits
AC Testing
AC Inputs during testing are driven at V CC - 0.5 V for a logic 1 and 0.45 V for a logic '0'. Timing measurements are made at V IHmin for a logic '1' and V ILmax for a logic '0'.
Input, Output Waveforms
Float Waveforms Semiconductor Group 324

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